[MISched] Use SchedRegion in overrideSchedPolicy and overridePostRASchedPolicy

llvm/include/llvm/CodeGen/MachineScheduler.h

@@ -65,6 +65,7 @@
 //
 // void <SubTarget>Subtarget::
 // overrideSchedPolicy(MachineSchedPolicy &Policy,
+//                     const MachineBasicBlock &MBB,
 //                     unsigned NumRegionInstrs) const {
 //   Policy.<Flag> = true;
 // }

llvm/include/llvm/CodeGen/TargetSubtargetInfo.h

@@ -16,6 +16,7 @@
 #include "llvm/ADT/ArrayRef.h"
 #include "llvm/ADT/SmallVector.h"
 #include "llvm/ADT/StringRef.h"
+#include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MacroFusion.h"
 #include "llvm/CodeGen/PBQPRAConstraint.h"
 #include "llvm/CodeGen/SchedulerRegistry.h"
@@ -231,6 +232,7 @@ class LLVM_ABI TargetSubtargetInfo : public MCSubtargetInfo {
   /// scheduling heuristics (no custom MachineSchedStrategy) to make
   /// changes to the generic scheduling policy.
   virtual void overrideSchedPolicy(MachineSchedPolicy &Policy,
+                                   const MachineBasicBlock &MBB,
                                    unsigned NumRegionInstrs) const {}
 
   /// Override generic post-ra scheduling policy within a region.
@@ -241,6 +243,7 @@ class LLVM_ABI TargetSubtargetInfo : public MCSubtargetInfo {
   /// Note that some options like tracking register pressure won't take effect
   /// in post-ra scheduling.
   virtual void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
+                                         const MachineBasicBlock &MBB,
                                          unsigned NumRegionInstrs) const {}
 
   // Perform target-specific adjustments to the latency of a schedule

llvm/lib/CodeGen/MachineScheduler.cpp

@@ -3703,6 +3703,7 @@ void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
                                   MachineBasicBlock::iterator End,
                                   unsigned NumRegionInstrs) {
   const MachineFunction &MF = *Begin->getMF();
+  const MachineBasicBlock &MBB = *Begin->getParent();
   const TargetLowering *TLI = MF.getSubtarget().getTargetLowering();
 
   // Avoid setting up the register pressure tracker for small regions to save
@@ -3725,7 +3726,7 @@ void GenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
   RegionPolicy.OnlyBottomUp = true;
 
   // Allow the subtarget to override default policy.
-  MF.getSubtarget().overrideSchedPolicy(RegionPolicy, NumRegionInstrs);
+  MF.getSubtarget().overrideSchedPolicy(RegionPolicy, MBB, NumRegionInstrs);
 
   // After subtarget overrides, apply command line options.
   if (!EnableRegPressure) {
@@ -4331,14 +4332,16 @@ void PostGenericScheduler::initPolicy(MachineBasicBlock::iterator Begin,
                                       MachineBasicBlock::iterator End,
                                       unsigned NumRegionInstrs) {
   const MachineFunction &MF = *Begin->getMF();
+  const MachineBasicBlock &MBB = *Begin->getParent();
 
   // Default to top-down because it was implemented first and existing targets
   // expect that behavior by default.
   RegionPolicy.OnlyTopDown = true;
   RegionPolicy.OnlyBottomUp = false;
 
   // Allow the subtarget to override default policy.
-  MF.getSubtarget().overridePostRASchedPolicy(RegionPolicy, NumRegionInstrs);
+  MF.getSubtarget().overridePostRASchedPolicy(RegionPolicy, MBB,
+                                              NumRegionInstrs);
 
   // After subtarget overrides, apply command line options.
   if (PostRADirection == MISched::TopDown) {

llvm/lib/Target/AArch64/AArch64Subtarget.cpp

@@ -534,6 +534,7 @@ unsigned AArch64Subtarget::classifyGlobalFunctionReference(
 }
 
 void AArch64Subtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
+                                           const MachineBasicBlock &MBB,
                                            unsigned NumRegionInstrs) const {
   // LNT run (at least on Cyclone) showed reasonably significant gains for
   // bi-directional scheduling. 253.perlbmk.

llvm/lib/Target/AArch64/AArch64Subtarget.h

@@ -343,6 +343,7 @@ class AArch64Subtarget final : public AArch64GenSubtargetInfo {
   }
 
   void overrideSchedPolicy(MachineSchedPolicy &Policy,
+                           const MachineBasicBlock &MBB,
                            unsigned NumRegionInstrs) const override;
   void adjustSchedDependency(SUnit *Def, int DefOpIdx, SUnit *Use, int UseOpIdx,
                              SDep &Dep,

llvm/lib/Target/AMDGPU/GCNSubtarget.cpp

@@ -324,6 +324,7 @@ bool GCNSubtarget::zeroesHigh16BitsOfDest(unsigned Opcode) const {
 }
 
 void GCNSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
+                                       const MachineBasicBlock &MBB,
                                        unsigned NumRegionInstrs) const {
   // Track register pressure so the scheduler can try to decrease
   // pressure once register usage is above the threshold defined by

llvm/lib/Target/AMDGPU/GCNSubtarget.h

@@ -1015,11 +1015,10 @@ class GCNSubtarget final : public AMDGPUGenSubtargetInfo,
   static bool hasHalfRate64Ops(const TargetSubtargetInfo &STI);
 
   // XXX - Why is this here if it isn't in the default pass set?
-  bool enableEarlyIfConversion() const override {
-    return true;
-  }
+  bool enableEarlyIfConversion() const override { return true; }
 
   void overrideSchedPolicy(MachineSchedPolicy &Policy,
+                           const MachineBasicBlock &MBB,
                            unsigned NumRegionInstrs) const override;
 
   void mirFileLoaded(MachineFunction &MF) const override;

llvm/lib/Target/PowerPC/PPCSubtarget.cpp

@@ -166,11 +166,12 @@ PPCGenSubtargetInfo::AntiDepBreakMode PPCSubtarget::getAntiDepBreakMode() const
 
 void PPCSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
   CriticalPathRCs.clear();
-  CriticalPathRCs.push_back(isPPC64() ?
-                            &PPC::G8RCRegClass : &PPC::GPRCRegClass);
+  CriticalPathRCs.push_back(isPPC64() ? &PPC::G8RCRegClass
+                                      : &PPC::GPRCRegClass);
 }
 
 void PPCSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
+                                       const MachineBasicBlock &MBB,
                                        unsigned NumRegionInstrs) const {
   // The GenericScheduler that we use defaults to scheduling bottom up only.
   // We want to schedule from both the top and the bottom and so we set

llvm/lib/Target/PowerPC/PPCSubtarget.h

@@ -240,6 +240,7 @@ class PPCSubtarget : public PPCGenSubtargetInfo {
   void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
 
   void overrideSchedPolicy(MachineSchedPolicy &Policy,
+                           const MachineBasicBlock &MBB,
                            unsigned NumRegionInstrs) const override;
   bool useAA() const override;
 

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

@@ -216,6 +216,7 @@ unsigned RISCVSubtarget::getMinimumJumpTableEntries() const {
 }
 
 void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
+                                         const MachineBasicBlock &MBB,
                                          unsigned NumRegionInstrs) const {
   // Do bidirectional scheduling since it provides a more balanced scheduling
   // leading to better performance. This will increase compile time.
@@ -232,6 +233,7 @@ void RISCVSubtarget::overrideSchedPolicy(MachineSchedPolicy &Policy,
 }
 
 void RISCVSubtarget::overridePostRASchedPolicy(MachineSchedPolicy &Policy,
+                                               const MachineBasicBlock &MBB,
                                                unsigned NumRegionInstrs) const {
   MISched::Direction PostRASchedDirection = getPostRASchedDirection();
   if (PostRASchedDirection == MISched::TopDown) {

llvm/lib/Target/RISCV/RISCVSubtarget.h

@@ -395,11 +395,13 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
   }
 
   void overrideSchedPolicy(MachineSchedPolicy &Policy,
+                           const MachineBasicBlock &MBB,
                            unsigned NumRegionInstrs) const override;
 
   void overridePostRASchedPolicy(MachineSchedPolicy &Policy,
+                                 const MachineBasicBlock &MBB,
                                  unsigned NumRegionInstrs) const override;
 };
-} // End llvm namespace
+} // namespace llvm
 
 #endif