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[RISCV] Teach SelectAddrRegRegScale that ADD is commutable. #149231

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merged 2 commits into from
Jul 17, 2025
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[RISCV] Teach SelectAddrRegRegScale that ADD is commutable. #149231

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bce9a7a
[RISCV] Teach SelectAddrRegRegScale that ADD is commutable.
topperc Jul 17, 2025
4b6a0ea
fixup! add comment
topperc Jul 17, 2025
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26 changes: 18 additions & 8 deletions llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -3058,17 +3058,27 @@ bool RISCVDAGToDAGISel::SelectAddrRegRegScale(SDValue Addr,
};

if (auto *C1 = dyn_cast<ConstantSDNode>(RHS)) {
// (add (add (shl A C2) B) C1) -> (add (add B C1) (shl A C2))
if (LHS.getOpcode() == ISD::ADD &&
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@svs-quic svs-quic Jul 17, 2025

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The outer add can be commutative as well? Are we handling the RHS.getOpcode() == ISD::ADD case?

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@topperc topperc Jul 17, 2025

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The outer add has a constant operand and we always canonicalize constants to the RHS.

SelectShl(LHS.getOperand(0), Index, Scale) &&
!isa<ConstantSDNode>(LHS.getOperand(1)) &&
isInt<12>(C1->getSExtValue())) {
// (add (add (shl A C2) B) C1) -> (add (add B C1) (shl A C2))
SDValue C1Val = CurDAG->getTargetConstant(*C1->getConstantIntValue(),
SDLoc(Addr), VT);
Base = SDValue(CurDAG->getMachineNode(RISCV::ADDI, SDLoc(Addr), VT,
LHS.getOperand(1), C1Val),
0);
return true;
if (SelectShl(LHS.getOperand(1), Index, Scale)) {
SDValue C1Val = CurDAG->getTargetConstant(*C1->getConstantIntValue(),
SDLoc(Addr), VT);
Base = SDValue(CurDAG->getMachineNode(RISCV::ADDI, SDLoc(Addr), VT,
LHS.getOperand(0), C1Val),
0);
return true;
}

if (SelectShl(LHS.getOperand(0), Index, Scale)) {
SDValue C1Val = CurDAG->getTargetConstant(*C1->getConstantIntValue(),
SDLoc(Addr), VT);
Base = SDValue(CurDAG->getMachineNode(RISCV::ADDI, SDLoc(Addr), VT,
LHS.getOperand(1), C1Val),
0);
return true;
}
}

// Don't match add with constants.
Expand Down
10 changes: 5 additions & 5 deletions llvm/test/CodeGen/RISCV/xqcisls.ll
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Expand Up @@ -309,8 +309,8 @@ define i64 @lrd(ptr %a, i32 %b) {
; RV32IZBAXQCISLS-LABEL: lrd:
; RV32IZBAXQCISLS: # %bb.0:
; RV32IZBAXQCISLS-NEXT: qc.lrw a2, a0, a1, 3
; RV32IZBAXQCISLS-NEXT: sh3add a0, a1, a0
; RV32IZBAXQCISLS-NEXT: lw a1, 4(a0)
; RV32IZBAXQCISLS-NEXT: addi a0, a0, 4
; RV32IZBAXQCISLS-NEXT: qc.lrw a1, a0, a1, 3
; RV32IZBAXQCISLS-NEXT: add a0, a2, a2
; RV32IZBAXQCISLS-NEXT: sltu a2, a0, a2
; RV32IZBAXQCISLS-NEXT: add a1, a1, a1
Expand Down Expand Up @@ -473,10 +473,10 @@ define void @srd(ptr %a, i32 %b, i64 %c) {
; RV32IZBAXQCISLS-NEXT: add a4, a2, a2
; RV32IZBAXQCISLS-NEXT: add a3, a3, a3
; RV32IZBAXQCISLS-NEXT: sltu a2, a4, a2
; RV32IZBAXQCISLS-NEXT: add a2, a3, a2
; RV32IZBAXQCISLS-NEXT: sh3add a3, a1, a0
; RV32IZBAXQCISLS-NEXT: qc.srw a4, a0, a1, 3
; RV32IZBAXQCISLS-NEXT: sw a2, 4(a3)
; RV32IZBAXQCISLS-NEXT: add a2, a3, a2
; RV32IZBAXQCISLS-NEXT: addi a0, a0, 4
; RV32IZBAXQCISLS-NEXT: qc.srw a2, a0, a1, 3
; RV32IZBAXQCISLS-NEXT: ret
%1 = add i64 %c, %c
%2 = getelementptr i64, ptr %a, i32 %b
Expand Down
40 changes: 18 additions & 22 deletions llvm/test/CodeGen/RISCV/xtheadmemidx.ll
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Expand Up @@ -858,14 +858,13 @@ define i64 @lurwu(ptr %a, i32 %b) {
define i64 @lrd(ptr %a, i64 %b) {
; RV32XTHEADMEMIDX-LABEL: lrd:
; RV32XTHEADMEMIDX: # %bb.0:
; RV32XTHEADMEMIDX-NEXT: slli a2, a1, 3
; RV32XTHEADMEMIDX-NEXT: th.lrw a2, a0, a1, 3
; RV32XTHEADMEMIDX-NEXT: addi a0, a0, 4
; RV32XTHEADMEMIDX-NEXT: th.lrw a1, a0, a1, 3
; RV32XTHEADMEMIDX-NEXT: add a0, a0, a2
; RV32XTHEADMEMIDX-NEXT: lw a2, 4(a0)
; RV32XTHEADMEMIDX-NEXT: add a0, a1, a1
; RV32XTHEADMEMIDX-NEXT: sltu a1, a0, a1
; RV32XTHEADMEMIDX-NEXT: add a2, a2, a2
; RV32XTHEADMEMIDX-NEXT: add a1, a2, a1
; RV32XTHEADMEMIDX-NEXT: add a0, a2, a2
; RV32XTHEADMEMIDX-NEXT: sltu a2, a0, a2
; RV32XTHEADMEMIDX-NEXT: add a1, a1, a1
; RV32XTHEADMEMIDX-NEXT: add a1, a1, a2
; RV32XTHEADMEMIDX-NEXT: ret
;
; RV64XTHEADMEMIDX-LABEL: lrd:
Expand Down Expand Up @@ -908,14 +907,13 @@ define i64 @lrd_2(ptr %a, i64 %b) {
define i64 @lurd(ptr %a, i32 %b) {
; RV32XTHEADMEMIDX-LABEL: lurd:
; RV32XTHEADMEMIDX: # %bb.0:
; RV32XTHEADMEMIDX-NEXT: slli a2, a1, 3
; RV32XTHEADMEMIDX-NEXT: th.lrw a2, a0, a1, 3
; RV32XTHEADMEMIDX-NEXT: addi a0, a0, 4
; RV32XTHEADMEMIDX-NEXT: th.lrw a1, a0, a1, 3
; RV32XTHEADMEMIDX-NEXT: add a0, a0, a2
; RV32XTHEADMEMIDX-NEXT: lw a2, 4(a0)
; RV32XTHEADMEMIDX-NEXT: add a0, a1, a1
; RV32XTHEADMEMIDX-NEXT: sltu a1, a0, a1
; RV32XTHEADMEMIDX-NEXT: add a2, a2, a2
; RV32XTHEADMEMIDX-NEXT: add a1, a2, a1
; RV32XTHEADMEMIDX-NEXT: add a0, a2, a2
; RV32XTHEADMEMIDX-NEXT: sltu a2, a0, a2
; RV32XTHEADMEMIDX-NEXT: add a1, a1, a1
; RV32XTHEADMEMIDX-NEXT: add a1, a1, a2
; RV32XTHEADMEMIDX-NEXT: ret
;
; RV64XTHEADMEMIDX-LABEL: lurd:
Expand Down Expand Up @@ -1047,11 +1045,10 @@ define void @srd(ptr %a, i64 %b, i64 %c) {
; RV32XTHEADMEMIDX-NEXT: add a2, a3, a3
; RV32XTHEADMEMIDX-NEXT: add a4, a4, a4
; RV32XTHEADMEMIDX-NEXT: sltu a3, a2, a3
; RV32XTHEADMEMIDX-NEXT: add a3, a4, a3
; RV32XTHEADMEMIDX-NEXT: slli a4, a1, 3
; RV32XTHEADMEMIDX-NEXT: add a4, a0, a4
; RV32XTHEADMEMIDX-NEXT: th.srw a2, a0, a1, 3
; RV32XTHEADMEMIDX-NEXT: sw a3, 4(a4)
; RV32XTHEADMEMIDX-NEXT: add a3, a4, a3
; RV32XTHEADMEMIDX-NEXT: addi a0, a0, 4
; RV32XTHEADMEMIDX-NEXT: th.srw a3, a0, a1, 3
; RV32XTHEADMEMIDX-NEXT: ret
;
; RV64XTHEADMEMIDX-LABEL: srd:
Expand All @@ -1071,11 +1068,10 @@ define void @surd(ptr %a, i32 %b, i64 %c) {
; RV32XTHEADMEMIDX-NEXT: add a4, a2, a2
; RV32XTHEADMEMIDX-NEXT: add a3, a3, a3
; RV32XTHEADMEMIDX-NEXT: sltu a2, a4, a2
; RV32XTHEADMEMIDX-NEXT: add a2, a3, a2
; RV32XTHEADMEMIDX-NEXT: slli a3, a1, 3
; RV32XTHEADMEMIDX-NEXT: add a3, a0, a3
; RV32XTHEADMEMIDX-NEXT: th.srw a4, a0, a1, 3
; RV32XTHEADMEMIDX-NEXT: sw a2, 4(a3)
; RV32XTHEADMEMIDX-NEXT: add a2, a3, a2
; RV32XTHEADMEMIDX-NEXT: addi a0, a0, 4
; RV32XTHEADMEMIDX-NEXT: th.srw a2, a0, a1, 3
; RV32XTHEADMEMIDX-NEXT: ret
;
; RV64XTHEADMEMIDX-LABEL: surd:
Expand Down
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