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[InstCombine]PtrReplacer: Correctly handle select with unavailable operands #148829

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Merged
merged 3 commits into from
Jul 16, 2025
Merged

[InstCombine]PtrReplacer: Correctly handle select with unavailable operands #148829

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[InstCombine]PtrReplacer: Correctly handle select with unavailable op…
Pierre-vh Jul 15, 2025
29cb1e3
test nits
Pierre-vh Jul 15, 2025
0a1bb70
update test names, move them to ptr-replace-alloca.ll
Pierre-vh Jul 16, 2025
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28 changes: 21 additions & 7 deletions llvm/lib/Transforms/InstCombine/InstCombineLoadStoreAlloca.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -277,6 +277,15 @@ bool PointerReplacer::collectUsers() {
Worklist.emplace_back(I);
};

auto TryPushInstOperand = [&](Instruction *InstOp) {
if (!UsersToReplace.contains(InstOp)) {
if (!ValuesToRevisit.insert(InstOp))
return false;
Worklist.emplace_back(InstOp);
}
return true;
};

PushUsersToWorklist(&Root);
while (!Worklist.empty()) {
Instruction *Inst = Worklist.pop_back_val();
Expand Down Expand Up @@ -309,21 +318,26 @@ bool PointerReplacer::collectUsers() {
// incoming values.
Worklist.emplace_back(PHI);
for (unsigned Idx = 0; Idx < PHI->getNumIncomingValues(); ++Idx) {
auto *IncomingValue = cast<Instruction>(PHI->getIncomingValue(Idx));
if (UsersToReplace.contains(IncomingValue))
continue;
if (!ValuesToRevisit.insert(IncomingValue))
if (!TryPushInstOperand(cast<Instruction>(PHI->getIncomingValue(Idx))))
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@shiltian shiltian Jul 15, 2025

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This is not tested

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@gandhi56 gandhi56 Jul 15, 2025

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This is a NFC and is already being tested in AMDGPU/ptr-replace-alloca.ll

return false;
Worklist.emplace_back(IncomingValue);
}
} else if (auto *SI = dyn_cast<SelectInst>(Inst)) {
auto *TrueInst = dyn_cast<Instruction>(SI->getTrueValue());
auto *FalseInst = dyn_cast<Instruction>(SI->getFalseValue());
if (!TrueInst || !FalseInst)
return false;

UsersToReplace.insert(SI);
PushUsersToWorklist(SI);
if (isAvailable(TrueInst) && isAvailable(FalseInst)) {
UsersToReplace.insert(SI);
PushUsersToWorklist(SI);
continue;
}

// Push select back onto the stack, followed by unavailable true/false
// value.
Worklist.emplace_back(SI);
if (!TryPushInstOperand(TrueInst) || !TryPushInstOperand(FalseInst))
return false;
} else if (auto *GEP = dyn_cast<GetElementPtrInst>(Inst)) {
UsersToReplace.insert(GEP);
PushUsersToWorklist(GEP);
Expand Down
35 changes: 35 additions & 0 deletions llvm/test/Transforms/InstCombine/AMDGPU/ptr-replacer-select-addrspacecast-crash.ll
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@gandhi56 gandhi56 Jul 15, 2025

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These tests could be merged into AMDGPU/ptr-replace-alloca.ll

Original file line number Diff line number Diff line change
@@ -0,0 +1,35 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=instcombine < %s | FileCheck %s

; Crashed in IC PtrReplacer because an invalid select was generated with addrspace(4) and addrspace(5)
; operands.

define amdgpu_kernel void @eggs(ptr addrspace(4) byref([12 x i8]) align 16 %arg) {
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@gandhi56 gandhi56 Jul 15, 2025

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More descriptive function name, please.

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@shiltian shiltian Jul 15, 2025

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eggs and milk, I actually love it. :-D

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@gandhi56 gandhi56 Jul 15, 2025

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Sure, I don't mind as long as other tests are named bagel, croissant, etc. Consistent breakfast is key for a healthy compiler ;)

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@shiltian shiltian Jul 15, 2025

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no I was just kidding :-D

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@Pierre-vh Pierre-vh Jul 16, 2025

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In my defense, the first one came from -passes=metarenamer (which I always use on reduced test cases), but the second one is just me continuing the trend 😄

I'll update the test names

; CHECK-LABEL: define amdgpu_kernel void @eggs(
; CHECK-SAME: ptr addrspace(4) byref([12 x i8]) align 16 [[ARG:%.*]]) {
; CHECK-NEXT: [[BB:.*:]]
; CHECK-NEXT: ret void
;
bb:
%alloca = alloca i32, i32 0, align 8, addrspace(5)
%alloca1 = alloca [12 x i8], align 16, addrspace(5)
call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) %alloca1, ptr addrspace(4) %arg, i64 0, i1 false)
%select = select i1 false, ptr addrspace(5) %alloca1, ptr addrspace(5) %alloca
call void @llvm.memcpy.p0.p5.i64(ptr null, ptr addrspace(5) %select, i64 0, i1 false)
ret void
}

define amdgpu_kernel void @milk(ptr addrspace(4) byref([12 x i8]) align 16 %arg) {
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@gandhi56 gandhi56 Jul 15, 2025

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ditto

; CHECK-LABEL: define amdgpu_kernel void @milk(
; CHECK-SAME: ptr addrspace(4) byref([12 x i8]) align 16 [[ARG:%.*]]) {
; CHECK-NEXT: [[BB:.*:]]
; CHECK-NEXT: ret void
;
bb:
%alloca = alloca i32, i32 0, align 8, addrspace(5)
%alloca1 = alloca [12 x i8], align 16, addrspace(5)
call void @llvm.memcpy.p5.p4.i64(ptr addrspace(5) %alloca1, ptr addrspace(4) %arg, i64 0, i1 false)
%select = select i1 false, ptr addrspace(5) %alloca, ptr addrspace(5) %alloca1
call void @llvm.memcpy.p0.p5.i64(ptr null, ptr addrspace(5) %select, i64 0, i1 false)
ret void
}