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[RISCV][VLOPT] Add support for vrgather #148249

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Merged
merged 7 commits into from
Jul 16, 2025
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Merged

[RISCV][VLOPT] Add support for vrgather #148249

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32f3dfa
[RISCV][VLOPT] Add support for vrgather
mikhailramalho Jul 10, 2025
ea20a78
Update test
mikhailramalho Jul 10, 2025
768189d
Swap condition
mikhailramalho Jul 11, 2025
eed2358
Added tests
mikhailramalho Jul 15, 2025
26d06da
Update llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
mikhailramalho Jul 15, 2025
3af1b58
Fixed test name
mikhailramalho Jul 15, 2025
2dff00e
Merge branch 'main' into vlopt-vrgather
mikhailramalho Jul 16, 2025
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13 changes: 13 additions & 0 deletions llvm/lib/Target/RISCV/RISCVVLOptimizer.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -747,6 +747,14 @@ getOperandLog2EEW(const MachineOperand &MO, const MachineRegisterInfo *MRI) {
return TwoTimes ? MILog2SEW + 1 : MILog2SEW;
}

// Vector Register Gather with 16-bit Index Elements Instruction
// Dest and source data EEW=SEW. Index vector EEW=16.
case RISCV::VRGATHEREI16_VV: {
if (MO.getOperandNo() == 2)
return 4;
return MILog2SEW;
}

default:
return std::nullopt;
}
Expand Down Expand Up @@ -1051,6 +1059,11 @@ static bool isSupportedInstr(const MachineInstr &MI) {
case RISCV::VSLIDEDOWN_VI:
case RISCV::VSLIDE1UP_VX:
case RISCV::VFSLIDE1UP_VF:
// Vector Register Gather Instructions
case RISCV::VRGATHER_VI:
case RISCV::VRGATHER_VV:
case RISCV::VRGATHER_VX:
case RISCV::VRGATHEREI16_VV:
// Vector Single-Width Floating-Point Add/Subtract Instructions
case RISCV::VFADD_VF:
case RISCV::VFADD_VV:
Expand Down
12 changes: 4 additions & 8 deletions llvm/test/CodeGen/RISCV/rvv/vl-opt-instrs.ll
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Expand Up @@ -5476,9 +5476,8 @@ define <vscale x 4 x i32> @vrgather_vi(<vscale x 4 x i32> %a, <vscale x 4 x i32>
;
; VLOPT-LABEL: vrgather_vi:
; VLOPT: # %bb.0:
; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; VLOPT-NEXT: vrgather.vi v12, v8, 5
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; VLOPT-NEXT: vrgather.vi v12, v8, 5
; VLOPT-NEXT: vadd.vv v8, v12, v10
; VLOPT-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.iXLen(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen 5, iXLen -1)
Expand All @@ -5497,9 +5496,8 @@ define <vscale x 4 x i32> @vrgather_vv(<vscale x 4 x i32> %a, <vscale x 4 x i32>
;
; VLOPT-LABEL: vrgather_vv:
; VLOPT: # %bb.0:
; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; VLOPT-NEXT: vrgather.vv v12, v8, v10
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; VLOPT-NEXT: vrgather.vv v12, v8, v10
; VLOPT-NEXT: vadd.vv v8, v12, v8
; VLOPT-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vrgather.vv.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i32> %idx, iXLen -1)
Expand All @@ -5518,9 +5516,8 @@ define <vscale x 4 x i32> @vrgather_vx(<vscale x 4 x i32> %a, iXLen %idx, <vscal
;
; VLOPT-LABEL: vrgather_vx:
; VLOPT: # %bb.0:
; VLOPT-NEXT: vsetvli a2, zero, e32, m2, ta, ma
; VLOPT-NEXT: vrgather.vx v12, v8, a0
; VLOPT-NEXT: vsetvli zero, a1, e32, m2, ta, ma
; VLOPT-NEXT: vrgather.vx v12, v8, a0
; VLOPT-NEXT: vadd.vv v8, v12, v10
; VLOPT-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vrgather.vx.nxv4i32.iXLen(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, iXLen %idx, iXLen -1)
Expand All @@ -5539,9 +5536,8 @@ define <vscale x 4 x i32> @vrgatherei16_vv(<vscale x 4 x i32> %a, <vscale x 4 x
;
; VLOPT-LABEL: vrgatherei16_vv:
; VLOPT: # %bb.0:
; VLOPT-NEXT: vsetvli a1, zero, e32, m2, ta, ma
; VLOPT-NEXT: vrgatherei16.vv v12, v8, v10
; VLOPT-NEXT: vsetvli zero, a0, e32, m2, ta, ma
; VLOPT-NEXT: vrgatherei16.vv v12, v8, v10
; VLOPT-NEXT: vadd.vv v8, v12, v8
; VLOPT-NEXT: ret
%1 = call <vscale x 4 x i32> @llvm.riscv.vrgatherei16.vv.nxv4i32(<vscale x 4 x i32> poison, <vscale x 4 x i32> %a, <vscale x 4 x i16> %idx, iXLen -1)
Expand Down
59 changes: 59 additions & 0 deletions llvm/test/CodeGen/RISCV/rvv/vl-opt-op-info.mir
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Expand Up @@ -1801,4 +1801,63 @@ body: |
; CHECK-NEXT: %y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0 /* e8 */
%x:vr = PseudoVMSET_M_B8 -1, 0
%y:vr = PseudoVMAND_MM_B16 $noreg, %x, 1, 0
...
---
name: vrgatherei16_vv
body: |
bb.0:
; CHECK-LABEL: name: vrgatherei16_vv
; CHECK: early-clobber %x:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: %y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
%x:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0
%y:vr = PseudoVADD_VV_M1 $noreg, %x, $noreg, 1, 5 /* e32 */, 0
...
---
name: vrgatherei16_vv_incompatible_data_eew
body: |
bb.0:
; CHECK-LABEL: name: vrgatherei16_vv_incompatible_data_eew
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
%y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0
...
---
name: vrgatherei16_vv_compatible_index_eew
body: |
bb.0:
; CHECK-LABEL: name: vrgatherei16_vv_compatible_index_eew
; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, %x, 1, 5 /* e32 */, 0 /* tu, mu */
%x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
%y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, %x, 1, 5 /* e32 */, 0
...
---
name: vrgatherei16_vv_incompatible_dest_emul
body: |
bb.0:
; CHECK-LABEL: name: vrgatherei16_vv_incompatible_dest_emul
; CHECK: early-clobber %x:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: %y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
%x:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0
%y:vr = PseudoVADD_VV_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0
...
---
name: vrgatherei16_vv_incompatible_source_emul
body: |
bb.0:
; CHECK-LABEL: name: vrgatherei16_vv_incompatible_source_emul
; CHECK: %x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0 /* tu, mu */
; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0 /* tu, mu */
%x:vr = PseudoVADD_VV_MF2 $noreg, $noreg, $noreg, -1, 5 /* e32 */, 0
%y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, %x, $noreg, 1, 5 /* e32 */, 0
...
---
name: vrgatherei16_vv_incompatible_index_emul
body: |
bb.0:
; CHECK-LABEL: name: vrgatherei16_vv_incompatible_index_emul
; CHECK: %x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0 /* tu, mu */
; CHECK-NEXT: early-clobber %y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, %x, 1, 5 /* e32 */, 0 /* tu, mu */
%x:vr = PseudoVADD_VV_M1 $noreg, $noreg, $noreg, -1, 4 /* e16 */, 0
%y:vr = PseudoVRGATHEREI16_VV_M1_E32_MF2 $noreg, $noreg, %x, 1, 5 /* e32 */, 0
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