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[AMDGPU] Provide control to force VGPR MFMA form #148079

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Merged
merged 5 commits into from
Jul 18, 2025
Merged

[AMDGPU] Provide control to force VGPR MFMA form #148079

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554f486
[AMDGPU] Provide control over AGPR/VGPR MFMA form
jrbyrnes Jul 10, 2025
aec8ea7
Use binary flag
jrbyrnes Jul 11, 2025
a9377e4
Add test coverage for amdgpu-agpr-alloc vs amdgpu-mfma-vgpr-form
jrbyrnes Jul 11, 2025
4917b9c
Formatting
jrbyrnes Jul 11, 2025
7f89718
Add TODO comment
jrbyrnes Jul 14, 2025
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23 changes: 22 additions & 1 deletion llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -29,6 +29,24 @@ enum { MAX_LANES = 64 };

using namespace llvm;

namespace {
enum MFMARegClass {
Unspecified,
VGPR,
AGPR,
};
}

cl::opt<MFMARegClass>
MFMAForm("amdgpu-mfma-form", cl::Hidden,
cl::desc("Register class to use for Opc and Dest of MFMA. If "
"unspecified, default to compiler heuristics"),
cl::init(MFMARegClass::Unspecified),
cl::values(clEnumValN(MFMARegClass::VGPR, "vgpr",
"Use the VGPR MFMA form."),
clEnumValN(MFMARegClass::AGPR, "agpr",
"Use the VGPR MFMA form.")));

const GCNTargetMachine &getTM(const GCNSubtarget *STI) {
const SITargetLowering *TLI = STI->getTargetLowering();
return static_cast<const GCNTargetMachine &>(TLI->getTargetMachine());
Expand Down Expand Up @@ -70,11 +88,14 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F,
}

MayNeedAGPRs = ST.hasMAIInsts();
if (ST.hasGFX90AInsts() &&
if (MFMAForm == MFMARegClass::Unspecified && ST.hasGFX90AInsts() &&
ST.getMaxNumVGPRs(F) <= AMDGPU::VGPR_32RegClass.getNumRegs() &&
!mayUseAGPRs(F))
MayNeedAGPRs = false; // We will select all MAI with VGPR operands.

else if (MFMAForm != MFMARegClass::Unspecified)
MayNeedAGPRs = MFMAForm == MFMARegClass::AGPR;

if (AMDGPU::isChainCC(CC)) {
// Chain functions don't receive an SP from their caller, but are free to
// set one up. For now, we can use s32 to match what amdgpu_gfx functions
Expand Down
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