[SPIR-V] Tablegen instruction selection in SPIR-V Backend doesn't account for a pointer size of the target

[VyacheslavLevytskyy]

SPIR-V Backend uses notion of a pointer size of the target, most notably, in legalizer code, but Tablegen instruction selection in SPIR-V Backend doesn't account for a pointer size of the target. This leads to crashes in spirv64 environment (-mtriple=spirv64-unknown-unknown), for example, when we are trying to translate G_LOAD. Even worse is that the issue is intertwined with match patterns used for ASSIGN_TYPE pseudo instructions, with register, register classes and register banks. The following example shows a minimal set of instructions that is incompatible with existing approach to Tablegen instruction selection in SPIR-V Backend:

%struct = type { [3 x float] }

define spir_kernel void @bar(i1 %sw) {
entry:
  %var1 = alloca %struct
  %var2 = alloca %struct
  %elem1 = getelementptr inbounds [3 x float], ptr %var1, i64 0, i64 0
  %elem2 = getelementptr inbounds [3 x float], ptr %var2, i64 0, i64 1
  %elem = select i1 %sw, ptr %elem1, ptr %elem2
  %res = load float, ptr %elem
  ret void
}

Translation of this code would fail either during legalization, or on the instruction selection stage, depending on how we tweaked pre-legalization and on 32/64 choice of the target.

[VyacheslavLevytskyy]

Resolved by #88725