add pseudo instrs for 8 and 32 bit src/dst ccr moves and expand them …

…to 16 bit instrs
llvm · Oct 26, 2024 · dce4c57 · dce4c57
1 parent c320df4
commit dce4c57
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Showing 3 changed files with 30 additions and 6 deletions.
diff --git a/llvm/lib/Target/M68k/M68kExpandPseudo.cpp b/llvm/lib/Target/M68k/M68kExpandPseudo.cpp
@@ -189,8 +189,11 @@ bool M68kExpandPseudo::ExpandMI(MachineBasicBlock &MBB,
                                 MVT::i16);
 
   case M68k::MOV8cd:
+  case M68k::MOV32cd:
     return TII->ExpandCCR(MIB, /*IsToCCR=*/true);
+
   case M68k::MOV8dc:
+  case M68k::MOV32dc:
     return TII->ExpandCCR(MIB, /*IsToCCR=*/false);
 
   case M68k::MOVM8jm_P:

diff --git a/llvm/lib/Target/M68k/M68kInstrData.td b/llvm/lib/Target/M68k/M68kInstrData.td
@@ -385,12 +385,14 @@ class MxMoveToCCRPseudo<MxOperand MEMOp>
 
 let mayLoad = 1 in
 foreach AM = MxMoveSupportedAMs in {
+  def MOV32c # AM : MxMoveToCCRPseudo<!cast<MxOpBundle>("MxOp32AddrMode_"#AM).Op>;
   def MOV16c # AM : MxMoveToCCR<!cast<MxOpBundle>("MxOp16AddrMode_"#AM).Op,
                                 !cast<MxEncMemOp>("MxMoveSrcOpEnc_"#AM)>;
   def MOV8c # AM  : MxMoveToCCRPseudo<!cast<MxOpBundle>("MxOp8AddrMode_"#AM).Op>;
 } // foreach AM
 
 // Only data register is allowed.
+def MOV32cd : MxMoveToCCRPseudo<MxOp32AddrMode_d.Op>;
 def MOV16cd : MxMoveToCCR<MxOp16AddrMode_d.Op, MxMoveSrcOpEnc_d>;
 def MOV8cd  : MxMoveToCCRPseudo<MxOp8AddrMode_d.Op>;
 
@@ -423,6 +425,9 @@ class MxMoveFromCCRPseudo<MxOperand MEMOp>
 
 let mayStore = 1 in
 foreach AM = MxMoveSupportedAMs in {
+  def MOV32 # AM # c
+    : MxMoveFromCCR_M<!cast<MxOpBundle>("MxOp32AddrMode_"#AM).Op,
+                      !cast<MxEncMemOp>("MxMoveDstOpEnc_"#AM)>;
   def MOV16 # AM # c
     : MxMoveFromCCR_M<!cast<MxOpBundle>("MxOp16AddrMode_"#AM).Op,
                       !cast<MxEncMemOp>("MxMoveDstOpEnc_"#AM)>;
@@ -431,6 +436,7 @@ foreach AM = MxMoveSupportedAMs in {
 } // foreach AM
 
 // Only data register is allowed.
+def MOV32dc : MxMoveFromCCRPseudo<MxOp32AddrMode_d.Op>;
 def MOV16dc : MxMoveFromCCR_R;
 def MOV8dc  : MxMoveFromCCRPseudo<MxOp8AddrMode_d.Op>;
 

diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp
@@ -757,13 +757,28 @@ void M68kInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
   bool ToSR = DstReg == M68k::SR;
 
   if (FromCCR) {
-    assert(M68k::DR8RegClass.contains(DstReg) &&
-           "Need DR8 register to copy CCR");
-    Opc = M68k::MOV8dc;
+    if (M68k::DR8RegClass.contains(DstReg))
+      Opc = M68k::MOV8dc;
+    else if (M68k::DR16RegClass.contains(DstReg))
+      Opc = M68k::MOV16dc;
+    else if (M68k::DR32RegClass.contains(DstReg))
+      Opc = M68k::MOV32dc;
+    else {
+    LLVM_DEBUG(dbgs() << "Cannot copy CCR to " << RI.getName(DstReg) 
+                << "(" << RI.getRegClass(DstReg) << ")\n");
+    llvm_unreachable("Invalid register for MOVE from CCR");
+    }
   } else if (ToCCR) {
-    assert(M68k::DR8RegClass.contains(SrcReg) &&
-           "Need DR8 register to copy CCR");
-    Opc = M68k::MOV8cd;
+    if (M68k::DR8RegClass.contains(SrcReg))
+      Opc = M68k::MOV8cd;
+    else if (M68k::DR16RegClass.contains(SrcReg))
+      Opc = M68k::MOV16cd;
+    else if (M68k::DR32RegClass.contains(SrcReg))
+      Opc = M68k::MOV32cd;
+    else {
+      LLVM_DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg) << " to CCR" << '\n');
+      llvm_unreachable("Invalid register for MOVE to CCR");
+    }
   } else if (FromSR || ToSR)
     llvm_unreachable("Cannot emit SR copy instruction");