Cleanup of the two test cases.

llvm · Jul 24, 2024 · d23a9b4 · d23a9b4
1 parent db3f082
commit d23a9b4
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Showing 2 changed files with 3 additions and 3 deletions.
diff --git a/llvm/test/CodeGen/PowerPC/subreg-coalescer.mir b/llvm/test/CodeGen/PowerPC/subreg-coalescer.mir
@@ -1,5 +1,5 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 -x mir < %s \
+# RUN: llc -mtriple powerpc64le-unknown-linux-gnu -mcpu=pwr8 %s \
 # RUN:   -verify-coalescing --run-pass=register-coalescer -o - | FileCheck %s
 
 # Check that the register coalescer correctly handles merging live ranges over

diff --git a/llvm/test/CodeGen/X86/subreg-fail.mir b/llvm/test/CodeGen/X86/subreg-fail.mir
@@ -1,6 +1,6 @@
 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
-# RUN: llc -mtriple x86_64-unknown-unknown -x mir < %s \
-# RUN:   -verify-coalescing -enable-subreg-liveness=true \
+# RUN: llc -mtriple x86_64-unknown-unknown %s \
+# RUN:   -verify-coalescing -enable-subreg-liveness \
 # RUN:   --run-pass=register-coalescer -o - | FileCheck %s
 
 # Check that the register coalescer correctly handles merging live ranges over