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[VectorCombine] fix insertion point of shuffles
As shown in issue #60649, the new shuffles were being inserted before a phi, and that is invalid. It seems like most test coverage for this fold (foldSelectShuffle) lives in the AArch64 dir, but this doesn't repro there for a base target.
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py | ||
; RUN: opt < %s -passes=vector-combine -S -mtriple=x86_64-- | FileCheck %s | ||
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target datalayout = "e-p:64:64-i64:64-f80:128-n8:16:32:64-S128" | ||
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; This would insert before a phi instruction which is invalid IR. | ||
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define <4 x double> @PR60649() { | ||
; CHECK-LABEL: @PR60649( | ||
; CHECK-NEXT: entry: | ||
; CHECK-NEXT: br label [[END:%.*]] | ||
; CHECK: unreachable: | ||
; CHECK-NEXT: br label [[END]] | ||
; CHECK: end: | ||
; CHECK-NEXT: [[T0:%.*]] = phi <4 x double> [ zeroinitializer, [[ENTRY:%.*]] ], [ zeroinitializer, [[UNREACHABLE:%.*]] ] | ||
; CHECK-NEXT: [[T1:%.*]] = phi <4 x double> [ zeroinitializer, [[ENTRY]] ], [ zeroinitializer, [[UNREACHABLE]] ] | ||
; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x double> [[T0]], <4 x double> [[T0]], <4 x i32> <i32 2, i32 3, i32 undef, i32 undef> | ||
; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x double> [[T0]], <4 x double> [[T0]], <4 x i32> <i32 0, i32 1, i32 undef, i32 undef> | ||
; CHECK-NEXT: [[TMP2:%.*]] = fdiv <4 x double> [[TMP1]], <double 0.000000e+00, double 0.000000e+00, double undef, double undef> | ||
; CHECK-NEXT: [[TMP3:%.*]] = fmul <4 x double> [[TMP0]], <double 0.000000e+00, double 0.000000e+00, double undef, double undef> | ||
; CHECK-NEXT: [[T5:%.*]] = shufflevector <4 x double> [[TMP2]], <4 x double> [[TMP3]], <4 x i32> <i32 0, i32 1, i32 4, i32 5> | ||
; CHECK-NEXT: ret <4 x double> [[T5]] | ||
; | ||
entry: | ||
br label %end | ||
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unreachable: | ||
br label %end | ||
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end: | ||
%t0 = phi <4 x double> [ zeroinitializer, %entry ], [ zeroinitializer, %unreachable ] | ||
%t1 = phi <4 x double> [ zeroinitializer, %entry ], [ zeroinitializer, %unreachable ] | ||
%t2 = shufflevector <4 x double> zeroinitializer, <4 x double> zeroinitializer, <4 x i32> <i32 0, i32 0, i32 1, i32 1> | ||
%t3 = fdiv <4 x double> %t0, %t2 | ||
%t4 = fmul <4 x double> %t0, %t2 | ||
%t5 = shufflevector <4 x double> %t3, <4 x double> %t4, <4 x i32> <i32 0, i32 1, i32 6, i32 7> | ||
ret <4 x double> %t5 | ||
} |