Revert "[X86] Support EGPR (R16-R31) for APX (#67702)"

This reverts commit feea5db. This causes significant compile-time regressions, even if EGPR is not used.
llvm · Oct 10, 2023 · 8cc2b51 · 8cc2b51
1 parent 3359adf
commit 8cc2b51
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Showing 17 changed files with 47 additions and 1,568 deletions.
diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h
@@ -1208,43 +1208,6 @@ namespace X86II {
     return false;
   }
 
-  inline bool canUseApxExtendedReg(const MCInstrDesc &Desc) {
-    uint64_t TSFlags = Desc.TSFlags;
-    uint64_t Encoding = TSFlags & EncodingMask;
-    // EVEX can always use egpr.
-    if (Encoding == X86II::EVEX)
-      return true;
-
-    // To be conservative, egpr is not used for all pseudo instructions
-    // because we are not sure what instruction it will become.
-    // FIXME: Could we improve it in X86ExpandPseudo?
-    if (isPseudo(TSFlags))
-      return false;
-
-    // MAP OB/TB in legacy encoding space can always use egpr except
-    // XSAVE*/XRSTOR*.
-    unsigned Opcode = Desc.Opcode;
-    switch (Opcode) {
-    default:
-      break;
-    case X86::XSAVE:
-    case X86::XSAVE64:
-    case X86::XSAVEOPT:
-    case X86::XSAVEOPT64:
-    case X86::XSAVEC:
-    case X86::XSAVEC64:
-    case X86::XSAVES:
-    case X86::XSAVES64:
-    case X86::XRSTOR:
-    case X86::XRSTOR64:
-    case X86::XRSTORS:
-    case X86::XRSTORS64:
-      return false;
-    }
-    uint64_t OpMap = TSFlags & X86II::OpMapMask;
-    return !Encoding && (OpMap == X86II::OB || OpMap == X86II::TB);
-  }
-
   /// \returns true if the MemoryOperand is a 32 extended (zmm16 or higher)
   /// registers, e.g. zmm21, etc.
   static inline bool is32ExtendedReg(unsigned RegNo) {

diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
@@ -331,8 +331,6 @@ def FeatureMOVDIRI  : SubtargetFeature<"movdiri", "HasMOVDIRI", "true",
                                        "Support movdiri instruction (direct store integer)">;
 def FeatureMOVDIR64B : SubtargetFeature<"movdir64b", "HasMOVDIR64B", "true",
                                         "Support movdir64b instruction (direct store 64 bytes)">;
-def FeatureEGPR : SubtargetFeature<"egpr", "HasEGPR", "true",
-                                   "Support extended general purpose register">;
 
 // Ivy Bridge and newer processors have enhanced REP MOVSB and STOSB (aka
 // "string operations"). See "REP String Enhancement" in the Intel Software

diff --git a/llvm/lib/Target/X86/X86InstrInfo.cpp b/llvm/lib/Target/X86/X86InstrInfo.cpp
@@ -92,37 +92,6 @@ X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
       Subtarget(STI), RI(STI.getTargetTriple()) {
 }
 
-const TargetRegisterClass *
-X86InstrInfo::getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
-                          const TargetRegisterInfo *TRI,
-                          const MachineFunction &MF) const {
-  auto *RC = TargetInstrInfo::getRegClass(MCID, OpNum, TRI, MF);
-  // If the target does not have egpr, then r16-r31 will be resereved for all
-  // instructions.
-  if (!RC || !Subtarget.hasEGPR())
-    return RC;
-
-  if (X86II::canUseApxExtendedReg(MCID))
-    return RC;
-
-  switch (RC->getID()) {
-  default:
-    return RC;
-  case X86::GR8RegClassID:
-    return &X86::GR8_NOREX2RegClass;
-  case X86::GR16RegClassID:
-    return &X86::GR16_NOREX2RegClass;
-  case X86::GR32RegClassID:
-    return &X86::GR32_NOREX2RegClass;
-  case X86::GR64RegClassID:
-    return &X86::GR64_NOREX2RegClass;
-  case X86::GR32_NOSPRegClassID:
-    return &X86::GR32_NOREX2_NOSPRegClass;
-  case X86::GR64_NOSPRegClassID:
-    return &X86::GR64_NOREX2_NOSPRegClass;
-  }
-}
-
 bool
 X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
                                     Register &SrcReg, Register &DstReg,

diff --git a/llvm/lib/Target/X86/X86InstrInfo.h b/llvm/lib/Target/X86/X86InstrInfo.h
@@ -150,17 +150,6 @@ class X86InstrInfo final : public X86GenInstrInfo {
 public:
   explicit X86InstrInfo(X86Subtarget &STI);
 
-  /// Given a machine instruction descriptor, returns the register
-  /// class constraint for OpNum, or NULL. Returned register class
-  /// may be different from the definition in the TD file, e.g.
-  /// GR*RegClass (definition in TD file)
-  /// ->
-  /// GR*_NOREX2RegClass (Returned register class)
-  const TargetRegisterClass *
-  getRegClass(const MCInstrDesc &MCID, unsigned OpNum,
-              const TargetRegisterInfo *TRI,
-              const MachineFunction &MF) const override;
-
   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
   /// such, whenever a client has an instance of instruction info, it should
   /// always be able to get register info as well (through this method).

diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp
@@ -158,10 +158,6 @@ X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
     case X86::GR16RegClassID:
     case X86::GR32RegClassID:
     case X86::GR64RegClassID:
-    case X86::GR8_NOREX2RegClassID:
-    case X86::GR16_NOREX2RegClassID:
-    case X86::GR32_NOREX2RegClassID:
-    case X86::GR64_NOREX2RegClassID:
     case X86::RFP32RegClassID:
     case X86::RFP64RegClassID:
     case X86::RFP80RegClassID:
@@ -614,14 +610,6 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
     }
   }
 
-  // Reserve the extended general purpose registers.
-  if (!Is64Bit || !MF.getSubtarget<X86Subtarget>().hasEGPR()) {
-    for (unsigned n = 0; n != 16; ++n) {
-      for (MCRegAliasIterator AI(X86::R16 + n, this, true); AI.isValid(); ++AI)
-        Reserved.set(*AI);
-    }
-  }
-
   assert(checkAllSuperRegsMarked(Reserved,
                                  {X86::SIL, X86::DIL, X86::BPL, X86::SPL,
                                   X86::SIH, X86::DIH, X86::BPH, X86::SPH}));