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llvm · Nov 28, 2024 · 7e0b7a8 · 7e0b7a8
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Showing 26 changed files with 681 additions and 151 deletions.
diff --git a/clang/lib/Basic/Targets/SystemZ.h b/clang/lib/Basic/Targets/SystemZ.h
@@ -107,9 +107,7 @@ class LLVM_LIBRARY_VISIBILITY SystemZTargetInfo : public TargetInfo {
 
   unsigned getMinGlobalAlign(uint64_t Size, bool HasNonWeakDef) const override;
 
-  bool useFP16ConversionIntrinsics() const override {
-    return false;
-  }
+  bool useFP16ConversionIntrinsics() const override { return false; }
 
   void getTargetDefines(const LangOptions &Opts,
                         MacroBuilder &Builder) const override;

diff --git a/clang/lib/CodeGen/Targets/SystemZ.cpp b/clang/lib/CodeGen/Targets/SystemZ.cpp
@@ -185,7 +185,7 @@ bool SystemZABIInfo::isFPArgumentType(QualType Ty) const {
 
   if (const BuiltinType *BT = Ty->getAs<BuiltinType>())
     switch (BT->getKind()) {
-    case BuiltinType::Float16:  // _Float16
+    case BuiltinType::Float16: // _Float16
     case BuiltinType::Float:
     case BuiltinType::Double:
       return true;
@@ -450,9 +450,9 @@ ABIArgInfo SystemZABIInfo::classifyArgumentType(QualType Ty) const {
     if (isFPArgumentType(SingleElementTy)) {
       assert(Size == 16 || Size == 32 || Size == 64);
       return ABIArgInfo::getDirect(
-          Size == 16 ? llvm::Type::getHalfTy(getVMContext())
-                     : Size == 32 ? llvm::Type::getFloatTy(getVMContext())
-                                  : llvm::Type::getDoubleTy(getVMContext()));
+          Size == 16   ? llvm::Type::getHalfTy(getVMContext())
+          : Size == 32 ? llvm::Type::getFloatTy(getVMContext())
+                       : llvm::Type::getDoubleTy(getVMContext()));
     } else {
       llvm::IntegerType *PassTy = llvm::IntegerType::get(getVMContext(), Size);
       return Size <= 32 ? ABIArgInfo::getNoExtend(PassTy)

diff --git a/clang/test/CodeGen/SystemZ/systemz-inline-asm.c b/clang/test/CodeGen/SystemZ/systemz-inline-asm.c
@@ -106,6 +106,14 @@ void test_M(void) {
 // CHECK: call void asm sideeffect "#FOO $0", "M"(i32 2147483647)
 }
 
+_Float16 test_f16(_Float16 a) {
+  _Float16 f;
+  asm("ler %0, %1" : "=f" (f) : "f" (a));
+  return f;
+// CHECK-LABEL: define{{.*}} half @test_f16(half noundef %a)
+// CHECK: call half asm "ler $0, $1", "=f,f"(half %a)
+}
+
 float test_f32(float f, float g) {
   asm("aebr %0, %2" : "=f" (f) : "0" (f), "f" (g));
   return f;

diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst
@@ -5555,7 +5555,7 @@ SystemZ:
   address context evaluates as zero).
 - ``h``: A 32-bit value in the high part of a 64bit data register
   (LLVM-specific)
-- ``f``: A 32, 64, or 128-bit floating-point register.
+- ``f``: A 16, 32, 64, or 128-bit floating-point register.
 
 X86:
 

diff --git a/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp b/llvm/lib/Target/SystemZ/AsmParser/SystemZAsmParser.cpp
@@ -888,6 +888,7 @@ ParseStatus SystemZAsmParser::parseRegister(OperandVector &Operands,
     return ParseStatus::NoMatch;
 
   // Determine the LLVM register number according to Kind.
+  // clang-format off
   const unsigned *Regs;
   switch (Kind) {
   case GR32Reg:  Regs = SystemZMC::GR32Regs;  break;
@@ -905,6 +906,7 @@ ParseStatus SystemZAsmParser::parseRegister(OperandVector &Operands,
   case AR32Reg:  Regs = SystemZMC::AR32Regs;  break;
   case CR64Reg:  Regs = SystemZMC::CR64Regs;  break;
   }
+  // clang-format on
   if (Regs[Reg.Num] == 0)
     return Error(Reg.StartLoc, "invalid register pair");
 

diff --git a/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp b/llvm/lib/Target/SystemZ/MCTargetDesc/SystemZMCTargetDesc.cpp
@@ -34,118 +34,96 @@ using namespace llvm;
 #include "SystemZGenRegisterInfo.inc"
 
 const unsigned SystemZMC::GR32Regs[16] = {
-  SystemZ::R0L, SystemZ::R1L, SystemZ::R2L, SystemZ::R3L,
-  SystemZ::R4L, SystemZ::R5L, SystemZ::R6L, SystemZ::R7L,
-  SystemZ::R8L, SystemZ::R9L, SystemZ::R10L, SystemZ::R11L,
-  SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L
-};
+    SystemZ::R0L,  SystemZ::R1L,  SystemZ::R2L,  SystemZ::R3L,
+    SystemZ::R4L,  SystemZ::R5L,  SystemZ::R6L,  SystemZ::R7L,
+    SystemZ::R8L,  SystemZ::R9L,  SystemZ::R10L, SystemZ::R11L,
+    SystemZ::R12L, SystemZ::R13L, SystemZ::R14L, SystemZ::R15L};
 
 const unsigned SystemZMC::GRH32Regs[16] = {
-  SystemZ::R0H, SystemZ::R1H, SystemZ::R2H, SystemZ::R3H,
-  SystemZ::R4H, SystemZ::R5H, SystemZ::R6H, SystemZ::R7H,
-  SystemZ::R8H, SystemZ::R9H, SystemZ::R10H, SystemZ::R11H,
-  SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H
-};
+    SystemZ::R0H,  SystemZ::R1H,  SystemZ::R2H,  SystemZ::R3H,
+    SystemZ::R4H,  SystemZ::R5H,  SystemZ::R6H,  SystemZ::R7H,
+    SystemZ::R8H,  SystemZ::R9H,  SystemZ::R10H, SystemZ::R11H,
+    SystemZ::R12H, SystemZ::R13H, SystemZ::R14H, SystemZ::R15H};
 
 const unsigned SystemZMC::GR64Regs[16] = {
-  SystemZ::R0D, SystemZ::R1D, SystemZ::R2D, SystemZ::R3D,
-  SystemZ::R4D, SystemZ::R5D, SystemZ::R6D, SystemZ::R7D,
-  SystemZ::R8D, SystemZ::R9D, SystemZ::R10D, SystemZ::R11D,
-  SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D
-};
+    SystemZ::R0D,  SystemZ::R1D,  SystemZ::R2D,  SystemZ::R3D,
+    SystemZ::R4D,  SystemZ::R5D,  SystemZ::R6D,  SystemZ::R7D,
+    SystemZ::R8D,  SystemZ::R9D,  SystemZ::R10D, SystemZ::R11D,
+    SystemZ::R12D, SystemZ::R13D, SystemZ::R14D, SystemZ::R15D};
 
 const unsigned SystemZMC::GR128Regs[16] = {
-  SystemZ::R0Q, 0, SystemZ::R2Q, 0,
-  SystemZ::R4Q, 0, SystemZ::R6Q, 0,
-  SystemZ::R8Q, 0, SystemZ::R10Q, 0,
-  SystemZ::R12Q, 0, SystemZ::R14Q, 0
-};
+    SystemZ::R0Q, 0, SystemZ::R2Q,  0, SystemZ::R4Q,  0, SystemZ::R6Q,  0,
+    SystemZ::R8Q, 0, SystemZ::R10Q, 0, SystemZ::R12Q, 0, SystemZ::R14Q, 0};
 
 const unsigned SystemZMC::FP16Regs[16] = {
-  SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H,
-  SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H,
-  SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H,
-  SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H
-};
+    SystemZ::F0H,  SystemZ::F1H,  SystemZ::F2H,  SystemZ::F3H,
+    SystemZ::F4H,  SystemZ::F5H,  SystemZ::F6H,  SystemZ::F7H,
+    SystemZ::F8H,  SystemZ::F9H,  SystemZ::F10H, SystemZ::F11H,
+    SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H};
 
 const unsigned SystemZMC::FP32Regs[16] = {
-  SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S,
-  SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S,
-  SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
-  SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S
-};
+    SystemZ::F0S,  SystemZ::F1S,  SystemZ::F2S,  SystemZ::F3S,
+    SystemZ::F4S,  SystemZ::F5S,  SystemZ::F6S,  SystemZ::F7S,
+    SystemZ::F8S,  SystemZ::F9S,  SystemZ::F10S, SystemZ::F11S,
+    SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S};
 
 const unsigned SystemZMC::FP64Regs[16] = {
-  SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D,
-  SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D,
-  SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
-  SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D
-};
+    SystemZ::F0D,  SystemZ::F1D,  SystemZ::F2D,  SystemZ::F3D,
+    SystemZ::F4D,  SystemZ::F5D,  SystemZ::F6D,  SystemZ::F7D,
+    SystemZ::F8D,  SystemZ::F9D,  SystemZ::F10D, SystemZ::F11D,
+    SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D};
 
 const unsigned SystemZMC::FP128Regs[16] = {
-  SystemZ::F0Q, SystemZ::F1Q, 0, 0,
-  SystemZ::F4Q, SystemZ::F5Q, 0, 0,
-  SystemZ::F8Q, SystemZ::F9Q, 0, 0,
-  SystemZ::F12Q, SystemZ::F13Q, 0, 0
-};
+    SystemZ::F0Q, SystemZ::F1Q, 0, 0, SystemZ::F4Q,  SystemZ::F5Q,  0, 0,
+    SystemZ::F8Q, SystemZ::F9Q, 0, 0, SystemZ::F12Q, SystemZ::F13Q, 0, 0};
 
 const unsigned SystemZMC::VR16Regs[32] = {
-  SystemZ::F0H, SystemZ::F1H, SystemZ::F2H, SystemZ::F3H,
-  SystemZ::F4H, SystemZ::F5H, SystemZ::F6H, SystemZ::F7H,
-  SystemZ::F8H, SystemZ::F9H, SystemZ::F10H, SystemZ::F11H,
-  SystemZ::F12H, SystemZ::F13H, SystemZ::F14H, SystemZ::F15H,
-  SystemZ::F16H, SystemZ::F17H, SystemZ::F18H, SystemZ::F19H,
-  SystemZ::F20H, SystemZ::F21H, SystemZ::F22H, SystemZ::F23H,
-  SystemZ::F24H, SystemZ::F25H, SystemZ::F26H, SystemZ::F27H,
-  SystemZ::F28H, SystemZ::F29H, SystemZ::F30H, SystemZ::F31H
-};
+    SystemZ::F0H,  SystemZ::F1H,  SystemZ::F2H,  SystemZ::F3H,  SystemZ::F4H,
+    SystemZ::F5H,  SystemZ::F6H,  SystemZ::F7H,  SystemZ::F8H,  SystemZ::F9H,
+    SystemZ::F10H, SystemZ::F11H, SystemZ::F12H, SystemZ::F13H, SystemZ::F14H,
+    SystemZ::F15H, SystemZ::F16H, SystemZ::F17H, SystemZ::F18H, SystemZ::F19H,
+    SystemZ::F20H, SystemZ::F21H, SystemZ::F22H, SystemZ::F23H, SystemZ::F24H,
+    SystemZ::F25H, SystemZ::F26H, SystemZ::F27H, SystemZ::F28H, SystemZ::F29H,
+    SystemZ::F30H, SystemZ::F31H};
 
 const unsigned SystemZMC::VR32Regs[32] = {
-  SystemZ::F0S, SystemZ::F1S, SystemZ::F2S, SystemZ::F3S,
-  SystemZ::F4S, SystemZ::F5S, SystemZ::F6S, SystemZ::F7S,
-  SystemZ::F8S, SystemZ::F9S, SystemZ::F10S, SystemZ::F11S,
-  SystemZ::F12S, SystemZ::F13S, SystemZ::F14S, SystemZ::F15S,
-  SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S,
-  SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S,
-  SystemZ::F24S, SystemZ::F25S, SystemZ::F26S, SystemZ::F27S,
-  SystemZ::F28S, SystemZ::F29S, SystemZ::F30S, SystemZ::F31S
-};
+    SystemZ::F0S,  SystemZ::F1S,  SystemZ::F2S,  SystemZ::F3S,  SystemZ::F4S,
+    SystemZ::F5S,  SystemZ::F6S,  SystemZ::F7S,  SystemZ::F8S,  SystemZ::F9S,
+    SystemZ::F10S, SystemZ::F11S, SystemZ::F12S, SystemZ::F13S, SystemZ::F14S,
+    SystemZ::F15S, SystemZ::F16S, SystemZ::F17S, SystemZ::F18S, SystemZ::F19S,
+    SystemZ::F20S, SystemZ::F21S, SystemZ::F22S, SystemZ::F23S, SystemZ::F24S,
+    SystemZ::F25S, SystemZ::F26S, SystemZ::F27S, SystemZ::F28S, SystemZ::F29S,
+    SystemZ::F30S, SystemZ::F31S};
 
 const unsigned SystemZMC::VR64Regs[32] = {
-  SystemZ::F0D, SystemZ::F1D, SystemZ::F2D, SystemZ::F3D,
-  SystemZ::F4D, SystemZ::F5D, SystemZ::F6D, SystemZ::F7D,
-  SystemZ::F8D, SystemZ::F9D, SystemZ::F10D, SystemZ::F11D,
-  SystemZ::F12D, SystemZ::F13D, SystemZ::F14D, SystemZ::F15D,
-  SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D,
-  SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D,
-  SystemZ::F24D, SystemZ::F25D, SystemZ::F26D, SystemZ::F27D,
-  SystemZ::F28D, SystemZ::F29D, SystemZ::F30D, SystemZ::F31D
-};
+    SystemZ::F0D,  SystemZ::F1D,  SystemZ::F2D,  SystemZ::F3D,  SystemZ::F4D,
+    SystemZ::F5D,  SystemZ::F6D,  SystemZ::F7D,  SystemZ::F8D,  SystemZ::F9D,
+    SystemZ::F10D, SystemZ::F11D, SystemZ::F12D, SystemZ::F13D, SystemZ::F14D,
+    SystemZ::F15D, SystemZ::F16D, SystemZ::F17D, SystemZ::F18D, SystemZ::F19D,
+    SystemZ::F20D, SystemZ::F21D, SystemZ::F22D, SystemZ::F23D, SystemZ::F24D,
+    SystemZ::F25D, SystemZ::F26D, SystemZ::F27D, SystemZ::F28D, SystemZ::F29D,
+    SystemZ::F30D, SystemZ::F31D};
 
 const unsigned SystemZMC::VR128Regs[32] = {
-  SystemZ::V0, SystemZ::V1, SystemZ::V2, SystemZ::V3,
-  SystemZ::V4, SystemZ::V5, SystemZ::V6, SystemZ::V7,
-  SystemZ::V8, SystemZ::V9, SystemZ::V10, SystemZ::V11,
-  SystemZ::V12, SystemZ::V13, SystemZ::V14, SystemZ::V15,
-  SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19,
-  SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23,
-  SystemZ::V24, SystemZ::V25, SystemZ::V26, SystemZ::V27,
-  SystemZ::V28, SystemZ::V29, SystemZ::V30, SystemZ::V31
-};
+    SystemZ::V0,  SystemZ::V1,  SystemZ::V2,  SystemZ::V3,  SystemZ::V4,
+    SystemZ::V5,  SystemZ::V6,  SystemZ::V7,  SystemZ::V8,  SystemZ::V9,
+    SystemZ::V10, SystemZ::V11, SystemZ::V12, SystemZ::V13, SystemZ::V14,
+    SystemZ::V15, SystemZ::V16, SystemZ::V17, SystemZ::V18, SystemZ::V19,
+    SystemZ::V20, SystemZ::V21, SystemZ::V22, SystemZ::V23, SystemZ::V24,
+    SystemZ::V25, SystemZ::V26, SystemZ::V27, SystemZ::V28, SystemZ::V29,
+    SystemZ::V30, SystemZ::V31};
 
 const unsigned SystemZMC::AR32Regs[16] = {
-  SystemZ::A0, SystemZ::A1, SystemZ::A2, SystemZ::A3,
-  SystemZ::A4, SystemZ::A5, SystemZ::A6, SystemZ::A7,
-  SystemZ::A8, SystemZ::A9, SystemZ::A10, SystemZ::A11,
-  SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15
-};
+    SystemZ::A0,  SystemZ::A1,  SystemZ::A2,  SystemZ::A3,
+    SystemZ::A4,  SystemZ::A5,  SystemZ::A6,  SystemZ::A7,
+    SystemZ::A8,  SystemZ::A9,  SystemZ::A10, SystemZ::A11,
+    SystemZ::A12, SystemZ::A13, SystemZ::A14, SystemZ::A15};
 
 const unsigned SystemZMC::CR64Regs[16] = {
-  SystemZ::C0, SystemZ::C1, SystemZ::C2, SystemZ::C3,
-  SystemZ::C4, SystemZ::C5, SystemZ::C6, SystemZ::C7,
-  SystemZ::C8, SystemZ::C9, SystemZ::C10, SystemZ::C11,
-  SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15
-};
+    SystemZ::C0,  SystemZ::C1,  SystemZ::C2,  SystemZ::C3,
+    SystemZ::C4,  SystemZ::C5,  SystemZ::C6,  SystemZ::C7,
+    SystemZ::C8,  SystemZ::C9,  SystemZ::C10, SystemZ::C11,
+    SystemZ::C12, SystemZ::C13, SystemZ::C14, SystemZ::C15};
 
 unsigned SystemZMC::getFirstReg(unsigned Reg) {
   static unsigned Map[SystemZ::NUM_TARGET_REGS];

diff --git a/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp b/llvm/lib/Target/SystemZ/SystemZAsmPrinter.cpp
@@ -138,6 +138,25 @@ static MCInst lowerSubvectorStore(const MachineInstr *MI, unsigned Opcode) {
     .addImm(0);
 }
 
+// MI extracts the first element of the source vector.
+static MCInst lowerVecEltExtraction(const MachineInstr *MI, unsigned Opcode) {
+  return MCInstBuilder(Opcode)
+      .addReg(SystemZMC::getRegAsGR64(MI->getOperand(0).getReg()))
+      .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()))
+      .addReg(0)
+      .addImm(0);
+}
+
+// MI inserts value into the first element of the destination vector.
+static MCInst lowerVecEltInsertion(const MachineInstr *MI, unsigned Opcode) {
+  return MCInstBuilder(Opcode)
+      .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
+      .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
+      .addReg(MI->getOperand(1).getReg())
+      .addReg(0)
+      .addImm(0);
+}
+
 // The XPLINK ABI requires that a no-op encoding the call type is emitted after
 // each call to a subroutine. This information can be used by the called
 // function to determine its entry point, e.g. for generating a backtrace. The
@@ -571,18 +590,19 @@ void SystemZAsmPrinter::emitInstruction(const MachineInstr *MI) {
     break;
 
   case SystemZ::LFER:
-    LoweredMI = MCInstBuilder(SystemZ::VLGVF)
-      .addReg(SystemZMC::getRegAsGR64(MI->getOperand(0).getReg()))
-      .addReg(SystemZMC::getRegAsVR128(MI->getOperand(1).getReg()))
-      .addReg(0).addImm(0);
+    LoweredMI = lowerVecEltExtraction(MI, SystemZ::VLGVF);
+    break;
+
+  case SystemZ::LFER_16:
+    LoweredMI = lowerVecEltExtraction(MI, SystemZ::VLGVH);
     break;
 
   case SystemZ::LEFR:
-    LoweredMI = MCInstBuilder(SystemZ::VLVGF)
-      .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
-      .addReg(SystemZMC::getRegAsVR128(MI->getOperand(0).getReg()))
-      .addReg(MI->getOperand(1).getReg())
-      .addReg(0).addImm(0);
+    LoweredMI = lowerVecEltInsertion(MI, SystemZ::VLVGF);
+    break;
+
+  case SystemZ::LEFR_16:
+    LoweredMI = lowerVecEltInsertion(MI, SystemZ::VLVGH);
     break;
 
 #define LOWER_LOW(NAME)                                                 \