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[ImportVerilog] Skip defparams which have been handled by slang. #7582

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merged 1 commit into from
Sep 4, 2024

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hailongSun2000
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For defparam, slang has propagated its value for the corresponding parameter. Such as:

module Top;
  Foo #(1) foo();
endmodule

module Foo #(
  parameter P = 32
);
  int a = P;
endmodule

module Bar;
  defparam Top.foo.P  = 4;
endmodule

On the AST, P and a both are 4. So we can skip defparam.

@hailongSun2000 hailongSun2000 merged commit f074d91 into llvm:main Sep 4, 2024
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@fabianschuiki
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Nice 🥳!

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2 participants