[arch][riscv][nuclei] Add Nuclei RISC-V processsor support

.travis.yml

@@ -22,6 +22,7 @@ env:
     - PROJECT=qemu-virt-riscv64-supervisor-test    TOOLCHAIN=riscv64-elf-7.5.0-Linux-x86_64
     - PROJECT=sifive-e-test             TOOLCHAIN=riscv32-elf-7.5.0-Linux-x86_64
     - PROJECT=sifive-unleashed-test     TOOLCHAIN=riscv64-elf-7.5.0-Linux-x86_64
+    - PROJECT=nuclei-hbird              TOOLCHAIN=riscv32-elf-7.5.0-Linux-x86_64
     - PROJECT=pc-x86-test               TOOLCHAIN=i386-elf-7.5.0-Linux-x86_64
     - PROJECT=pc-x86-64-test            TOOLCHAIN=x86_64-elf-7.5.0-Linux-x86_64
 

arch/riscv/arch.c

@@ -18,6 +18,11 @@
 
 #include "riscv_priv.h"
 
+#ifdef RISCV_VARIANT_NUCLEI
+#include <riscv_encoding.h>
+volatile unsigned long riscv_reschedule = 0;
+#endif
+
 #define LOCAL_TRACE 0
 
 // per cpu structure, pointed to by xscratch
@@ -35,6 +40,36 @@ void riscv_configure_percpu_early(uint hart_id) {
 
 // first C level code to initialize each cpu
 void riscv_early_init_percpu(void) {
+#ifdef RISCV_VARIANT_NUCLEI
+    extern void *vectab;
+    extern void exc_entry(void);
+    extern void irq_entry(void);
+    extern void _premain_init(void);
+    extern void platform_init_timer(void);
+    extern unsigned long default_stack_top;
+    unsigned long entry_tmp = 0;
+
+    // set nmi exception to mtvec
+    riscv_csr_set(CSR_MMISC_CTL, MMISC_CTL_NMI_CAUSE_FFF);
+    // set clic vector base
+    riscv_csr_write(CSR_MTVT, (uintptr_t)&vectab);
+    entry_tmp = ((unsigned long)irq_entry) | 0x1;
+    // set clic non-vector irq entry
+    riscv_csr_write(CSR_MTVT2, (uintptr_t)entry_tmp);
+    entry_tmp = (((unsigned long)exc_entry) & (~(0x3FUL))) | 0x3;
+    // set exception entry and enable clic mode
+    riscv_csr_write(CSR_MTVEC, (uintptr_t)entry_tmp);
+    // enable cycle and instret counter
+    riscv_csr_set(mcounteren, 0x5);
+    // set csr mscratch for interrupt stack usage
+
+    _premain_init();
+
+    platform_init_timer();
+    // mask all exceptions, just in case
+    riscv_csr_clear(RISCV_CSR_XSTATUS, RISCV_CSR_XSTATUS_IE);
+    riscv_csr_write(CSR_MSCRATCH, &default_stack_top);
+#else
     // set the top level exception handler
     riscv_csr_write(RISCV_CSR_XTVEC, (uintptr_t)&riscv_exception_entry);
 
@@ -44,6 +79,7 @@ void riscv_early_init_percpu(void) {
 
     // enable cycle counter (disabled for now, unimplemented on sifive-e)
     //riscv_csr_set(mcounteren, 1);
+#endif
 }
 
 // called very early just after entering C code on boot processor
@@ -62,6 +98,18 @@ void riscv_init_percpu(void) {
     riscv_csr_set(RISCV_CSR_XIE, RISCV_CSR_XIE_EIE);
 }
 
+#ifdef RISCV_VARIANT_NUCLEI
+void riscv_clic_irq_entry(void) {
+    THREAD_STATS_INC(interrupts);
+}
+
+void riscv_clic_irq_exit(bool reschedule) {
+    if (reschedule != INT_NO_RESCHEDULE) {
+        riscv_reschedule = reschedule;
+    }
+}
+#endif
+
 // called later once the kernel is running before platform and target init
 void arch_init(void) {
     riscv_init_percpu();