[arm] Ensure context switch doesn't happen from irq #280
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Context switches should not happen from within the interrupt context before interrupt is cleared by write to GIC EOIR register, without it GIC will simply keep that interrupt active even if the hardware source clears the interrupt to the gic, causing subsequent irqs from the source to not get delivered to the CPU. This change adds an assertion that context switch doesn't happen from irq context before interrupt is EOIed. TCB field is added to convey if the current thread has interrupt context active, if so thread_resched should ideally not get called. Signed-off-by: vannapurve [email protected]
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Accidentally closed #276 when trying to update my branch with mainline. Please assume the discussion to be in continuation of the above pull request. I have uploaded this patch to update support for just arm/arm64 archs for now. If this scheme looks ok, I can extend the support to other archs. Alternative scheme I was thinking about was some generic layer like kernel/thread.c exposing APIs to allow the bookkeeping of CPU IRQ context state which can be called from arch specific exception handlers, this can reduce code duplication in all the archs. |
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Context switches should not happen from within the interrupt
context before interrupt is cleared by write to GIC EOIR register,
without it GIC will simply keep that interrupt active even if
the hardware source clears the interrupt to the gic, causing
subsequent irqs from the source to not get delivered to the CPU.
This change adds an assertion that context switch doesn't happen
from irq context before interrupt is EOIed. TCB field is added
to convey if the current thread has interrupt context active, if
so thread_resched should ideally not get called.
Signed-off-by: vannapurve [email protected]