some parts are copy/pasted from https://github.com/cleverca22/rpi-open-firmware
which itself is a fork of https://github.com/christinaa/rpi-open-firmware

what works:
network booting lk.elf on an rpi4 (just rename to start4.elf and host over tftp)
the full console with line editing and history
serial over pl011 (but no serial init, relies on previous bootloader stage)
reboot command
irq handling for timer compare and uart
one-shot timer
reporting cpu exceptions such as divide by zero

… to 115200

…t build

add sdhost code
add gpio pullup test
fix peripheral address
implement batch gpio pull config changes
fix memory information to be based on boot stage, not model
add rpi4 recovery.bin support

This is a clean rewrite of the OTP routines using new findings.

Based on previous research, this commit implements a write command.

       Use with care!
What is done cannot be undone.

This bit does not tell whether programming was OK, but whether
programming is enabled. Renaming should prevent confusion when
BCM283x support is added.

The OTP chip in BCM283x cannot program a full word in a single
command. Instead, individual bits must be programmed one by one.

There is also a subtle difference in program enable. The magic
sequence must be written to OTP_BITSEL, not OTP_DATA.

Tested on a RPi3 B (no plus).

Enhance OTP handling

Get rid of hardcoded values in pll_control.c

It should not be modified, so it may go into read-only data.

This change allows reusing the data from other modules.

All PLLs have a 12-bit fractional part. There is no need to
complicate matters by defining per-PLL masks.

The definition of these functions is now trivial, so expose the
underlying get_pll_freq() and get_pll_chan_freq() instead.

The sense of the "dividers" is currently reversed:
- bit 14 / 11 in the ANA1 register _doubles_ the resulting PLL
  frequency,
- PDIV field in the PLL_CTRL register divides the resulting
  frequency by an integer

Some magic values must be written to the PLLx_DIG registers to take
a stopped PLL out of RESET.

It is also a good idea to hold all PLL channels while doing so.

The prescaler is either not present on a BCM2711, or it works
differently. For the record, the PLLC NDIV:FRAC divider is set up
to 3 GHz by the firmware as if there was no prescaler.

These bits are common to all CM_PLL registers.

Since the PDIV field and PRSTN bit are found on the same positions
in all PLLs, one single define is sufficient. It may even allow
some optimizations in the compiler.

This variable can be useful to any clock-related code, so let's
have the declaration in a common header file.

I'm quite confident now that this bit controls a prescaler in the
feedback loop, so give it a better name, so it cannot be confused
with the PDIV field.

Change the PLL frequency.

Quite useful to research the undocumented internal I2C bus on
BCM2711 (bus 7). For example, I can control the PWR LED on my RPi4B
like this:

Turn off:
  i2c_xfer 7 0x43 0504 0
Turn on:
  i2c_xfer 7 0x43 0500 0

The pre-configured I2C bus rate is too high for MxL7004 on a RPi4
after start4.elf is launched (over 900 kHz). The spec says the
maximum SCL clock frequency is 400 kHz, but the firmware uses an
even lower value (100 kHz).

FWIW 400 kHz does not work on my RPi4B, but maybe the default
FEDL/REDL calculation does not satisfy the SCL_H and/or SCL_L
period requirements of that chip. Who cares... just use 100 kHz.

it will bring up the DDR2 controller
then mount an ext2 fs on SD partition 2
then drop into a shell for testing

fix DPI clocks and hsync/vsync generation
implement HVS code

overhaul arch setup for targets
add support for .text.bootloader_state on the pi4

…bootloader hasnt initialized things