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[arch][arm64] remove an unnecessary call to arm64_el3_to_el1
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The existing arm64_elx_to_el1 already handles dropping the primary and
any secondary cpu down to el1 by the time this code path is reached.
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travisg committed Nov 10, 2024
1 parent 6e39e56 commit 52fa818
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Showing 3 changed files with 0 additions and 38 deletions.
6 changes: 0 additions & 6 deletions arch/arm64/arch.c
Original file line number Diff line number Diff line change
Expand Up @@ -31,12 +31,6 @@ static void arm64_cpu_early_init(void) {
/* set the vector base */
ARM64_WRITE_SYSREG(VBAR_EL1, (uint64_t)&arm64_exception_base);

/* switch to EL1 */
unsigned int current_el = ARM64_READ_SYSREG(CURRENTEL) >> 2;
if (current_el > 1) {
arm64_el3_to_el1();
}

arch_enable_fiqs();
}

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31 changes: 0 additions & 31 deletions arch/arm64/asm.S
Original file line number Diff line number Diff line change
Expand Up @@ -43,37 +43,6 @@ FUNCTION(arm64_context_switch)

ret

FUNCTION(arm64_el3_to_el1)
/* set EL2 to 64bit */
mrs x0, scr_el3
orr x0, x0, #(1<<10)
msr scr_el3, x0

/* set EL1 to 64bit */
mov x0, #(1<<31)
msr hcr_el2, x0

/* disable EL2 coprocessor traps */
mov x0, #0x33ff
msr cptr_el2, x0

/* disable EL1 FPU traps */
mov x0, #(0b11<<20)
msr cpacr_el1, x0

/* set up the EL1 bounce interrupt */
mov x0, sp
msr sp_el1, x0

adr x0, .Ltarget
msr elr_el3, x0

mov x0, #((0b1111 << 6) | (0b0101)) /* EL1h runlevel */
msr spsr_el3, x0
isb

eret

/* drop from whatever EL we may already be in to EL1.
* carefully avoids using x0-x3 since this is called from start.S
* which is trying to preserve them.
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1 change: 0 additions & 1 deletion arch/arm64/include/arch/arm64.h
Original file line number Diff line number Diff line change
Expand Up @@ -58,7 +58,6 @@ struct arm64_stackframe {

struct thread;
extern void arm64_exception_base(void);
void arm64_el3_to_el1(void);
void arm64_fpu_exception(struct arm64_iframe_long *iframe);
void arm64_fpu_save_state(struct thread *thread);

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