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initrd/bin/talos-init: send IPL complete message to BMC #1313

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merged 7 commits into from
Apr 3, 2023

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krystian-hebel
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BMC awaits this message before it takes control over CPU fans speed.

@tlaurion
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tlaurion commented Feb 15, 2023

@krystian-hebel now we talk! Thank you so much for PR pointing to coreboot and Heads changes.

Will test produced CircleCI binaries tomorrow and report back

@tlaurion
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@krystian-hebel can you just please have heads master circleci config as well so that builds are triggered automatically?

@tlaurion
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Or better, have CircleCI follow you Heads fork so that builds happens on your CircleCI time (not osresearch's). This is better for continuous contributors, while not an issue. Not sure what is the issue here?

@krystian-hebel
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@macpijan ^ can we do this?

@tlaurion
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tlaurion commented Feb 15, 2023

@krystian-hebel create a circleci account, linked with your github account.

Then in project screen on circleci, select heads as a project to be followed. Amend commit and force push. Enjoy circleci free hour build steps for free.

@tlaurion
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tlaurion commented Feb 17, 2023

@krystian-hebel Works, fan is slowed down upon early Heads init, (now talos-init pointing to gui-ini) as expected.


Tested:

Downloading artifacts from CircleCI:

user@talos-tests:~/QubesIncoming/heads-tests$ wget https://output.circle-artifacts.com/output/job/dcb7c8ab-bea4-4987-aa70-38e51cd79645/artifacts/0/build/ppc64/talos-2_server/heads-talos-2_server-v0.2.0-1371-gb137dd3-zImage.bundled https://output.circle-artifacts.com/output/job/dcb7c8ab-bea4-4987-aa70-38e51cd79645/artifacts/0/build/ppc64/talos-2_server/heads-talos-2_server-v0.2.0-1371-gb137dd3.bootblock  https://output.circle-artifacts.com/output/job/dcb7c8ab-bea4-4987-aa70-38e51cd79645/artifacts/0/build/ppc64/talos-2_server/heads-talos-2_server-v0.2.0-1371-gb137dd3.rom

Uploading artifacts:
rsync -ravczz --inplace --delete /home/user/QubesIncoming/heads-tests [email protected]:/tmp/images/

Testing firmware:

ssh -t -l root talos 'cd /tmp/images/heads-tests/ && pflash -r /tmp/talos.pnor && pflash  -F ../../talos.pnor -f -P HBB -p *bootblock* && pflash  -F ../../talos.pnor -f -P HBI -p *.rom* && pflash  -F ../../talos.pnor -f -P BOOTKERNEL -p *zImage.bundled* && mboxctl --backend file:/tmp/talos.pnor && echo "ALL GOOD! Booting and attaching BMC console" && obmcutil poweron && obmc-console-client'

Gives attached log:
log.txt

Exit to recovery shell from Heads to check CPU freq:

~ # cat /proc/cpuinfo | grep clock
clock		: 1833.000000MHz
clock		: 1833.000000MHz
clock		: 1833.000000MHz
clock		: 1833.000000MHz
clock		: 1833.000000MHz
clock		: 1833.000000MHz
clock		: 1833.000000MHz
clock		: 1833.000000MHz
clock		: 1833.000000MHz
clock		: 1833.000000MHz
clock		: 1833.000000MHz
clock		: 1833.000000MHz
clock		: 1833.000000MHz
clock		: 1833.000000MHz
clock		: 1833.000000MHz
clock		: 1833.000000MHz

@tlaurion
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@krystian-hebel Putting as draft since you said to me in upstream Dasharo/dasharo-issues#35 that this should not be merged (some TPM code might not be under this dasharo/coreboot commit).

Please poke me in next PR superseding this. Dasharo/dasharo-issues#35 can be closed meanwhile.

@tlaurion tlaurion marked this pull request as draft February 18, 2023 21:57
@tlaurion
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Will test alongside of #1339

@tlaurion
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Again didn't have time to test yet. But since changes here are considered maybe unstable, Would it be possible to simply rebase and use merged #1339 in the future?

TPM1/2 unification is merged under master now, so rebasing should happen anyway going further.

@krystian-hebel
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It does not work as expected, I'm debugging it now. I've found some rather unrelated errors in the process that would impact all non-x86 platforms, will create another PR with fixes soon.

@krystian-hebel
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I've updated this PR so my changes won't get lost (again), I know I still have to do a rebase.

@tlaurion how bad of an idea would be to push all coreboot commits related to Talos in form of patches to this repo? There are almost 200 commits right now, but some of them ("fix typo" kind) can be squashed.

@tlaurion
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@krystian-hebel why mot simply have modules/coreboot point to that squashed commit to dasharo/coreboot?

@krystian-hebel
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This is what we've been doing until now, but it proved to be hard to manage. Right now our last connection with upstream is from 2 years ago, with a lot to rebase, and it doesn't give us a clean way of changing one commit that was changed after review upstream. We would have to keep each release in a separate branch instead of tag, because each rebase results in a forced push. As we're getting close to production-ready version, we would like to make future maintenance as easy as possible, while we are still in pre-v1.0.0 and such changes are possible.

For PC Engines we had yet another approach, which worked great until changes were actually merged upstream. That left us with either empty commits or commits with just whitespace/variable name/comment style different in PC Engines repo than upstream. The purpose of that was slightly different, we knew that there would be some changes specific to those releases that wouldn't make sense for upstream, or at least we thought so at that time.

Now we want to see if patches would be better for this case. They would allow us to make changes to older commits while keeping those changes in history, instead of doing a hard rewrite. The same goes for preparation for upstream - all changes in one piece of logic are limited to one patch file, that can be modified without having to rebase every later commit, and more importantly, without adding separate commits for simple fixes. In some cases, squashing such fix isn't trivial and produces a conflict.

I will probably keep those patches somewhere anyway, I'm just asking if Heads may be where they live for now. I'll understand if you don't want to keep so many additional files, since this would stay forever in the git history, making this repo larger. I guess we can also keep a separate branch with patch-like commits, updated in parallel to our usual develop-release pair of branches.

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tlaurion commented Mar 28, 2023

Discussed off channel.

Possibilities are:

  • Have patches/coreboot-talos/*.patches or patches/coreboot-talos.patches (needing fixing of modules/coreboot module to not simply reuse coreboot-git which could cause problems in the future)
  • Have dasharo/coreboot-talos, or dasharo/coreboot-talos/devel or dasharo/coreboot/talos/devel branch containing talos master changes inside of it (there is mismatch as of now, some things are under master but not under devel, some under devel but not under master), so modules/coreboot can point to a commit where coreboot work happened upstream without heads needing to have patches as above point, with ever growing patches over time and maintainership additioanl costs and git history and size increase (the number of patches/coreboot* has decreased over time with local patches having been upstreamed to coreboot, and we like it that way. So ideally, dasharo/coreboot/dasharo/coreboot-talos would hold those changes and the tip commit of tested branch should be used)

I have no strong opinion against either of them, of course preferring coreboot work happening outside of Heads where heads can only refer to a commit/release tarball, as for all other modules. The only problem with actual modules/coreboot git approach as of now is foreseeing multiple boards abusing of the coreboot-git locally created directory, which could eventually be used for parallel builds of multiple boards. It would be better that Makefile+modules/coreboot could use a named approach for git clone directory, and that coreboot-git being named coreboot-talos in present case, where circleci config would point to coreboot-talos (as opposed to coreboot-git) for cache saving and reusal.

Ideally:

  • Heads changes are related to scripts, modules changes
  • modules/coreboot PR should change the above where needed pointing to coreboot tested commits and then merged under heads master.
  • dasharo/heads should branch heads master for dasharo/heads releases, pointing to heads tip commit used for release, containing both ppc64 modules needed changes (as of now outside of Makefile: readd util-linux dependency check to add agetty when needed #1353 which was removed by error, sorry about that but we should agree on working, tested state prior of dasharo release anyway) and modules/coreboot pointing to tested dasharo/coreboot tested working tip.

@krystian-hebel krystian-hebel force-pushed the talos_fan_speed branch 2 times, most recently from 293a31d to d8f6b08 Compare March 30, 2023 15:19
@krystian-hebel
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krystian-hebel commented Mar 30, 2023

@tlaurion could you test https://app.circleci.com/pipelines/github/Dasharo/heads/11/workflows/5d083562-57ae-4095-8c5c-b46b6cca4f8f/jobs/309/artifacts? Things to check:

  • cbmem -L works
  • cbmem -L shows ~17 entries (instead of 6)
  • fans are quiet

If everything is fine so far I'll proceed with rebasing. This also depends on #1352, for now I just cherry-picked that change here, but it would be nice if that PR gets merged first.

I also noticed that initrd/bin/talos-init gets executed twice, at least for server. I think this may be because it is started for two terminals (VGA + serial) on this platform, unless this is some known issue.

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@krystian-hebel this is with agetty back in?

@krystian-hebel
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@tlaurion I think this may even be before it was removed. I can use obmc-console-client through SSH without issues, haven't tested VGA.

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tlaurion commented Mar 30, 2023

Ok, I see 122 files changes differences between this and master.
Will test only for what yo urequested and wait for rebase for the rest.

But yeah, agetty is in without util-linux removed from Makefile so would not be impacted by this.
Makes sense that two init are called from init script hack to use agetty as defined on board config.

Once again, testing server board here since same as single talos board now in master.

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user@talos-tests:~$ cd /home/user/QubesIncoming/heads-tests
user@talos-tests:~/QubesIncoming/heads-tests$ ls
heads-talos-2_server-v0.2.0-1371-gb137dd3.bootblock
heads-talos-2_server-v0.2.0-1371-gb137dd3.rom
heads-talos-2_server-v0.2.0-1371-gb137dd3-zImage.bundled
log.txt
user@talos-tests:~/QubesIncoming/heads-tests$ rm *
user@talos-tests:~/QubesIncoming/heads-tests$ wget https://output.circle-artifacts.com/output/job/2e643375-fb95-492b-8a39-9e80d4df56cc/artifacts/0/build/ppc64/talos-2_server/heads-talos-2_server-v0.2.0-1377-gd8f6b08-zImage.bundled https://output.circle-artifacts.com/output/job/2e643375-fb95-492b-8a39-9e80d4df56cc/artifacts/0/build/ppc64/talos-2_server/heads-talos-2_server-v0.2.0-1377-gd8f6b08.bootblock https://output.circle-artifacts.com/output/job/2e643375-fb95-492b-8a39-9e80d4df56cc/artifacts/0/build/ppc64/talos-2_server/heads-talos-2_server-v0.2.0-1377-gd8f6b08.rom
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Resolving circleci-tasks-prod.s3.us-east-1.amazonaws.com (circleci-tasks-prod.s3.us-east-1.amazonaws.com)... 52.217.43.184, 52.217.123.170, 52.217.232.74, ...
Connecting to circleci-tasks-prod.s3.us-east-1.amazonaws.com (circleci-tasks-prod.s3.us-east-1.amazonaws.com)|52.217.43.184|:443... connected.
HTTP request sent, awaiting response... 200 OK
Length: 12300632 (12M) [application/octet-stream]
Saving to: ‘heads-talos-2_server-v0.2.0-1377-gd8f6b08-zImage.bundled’

heads-talos-2_serve 100%[===================>]  11.73M  2.69MB/s    in 4.5s    

2023-03-30 13:30:16 (2.63 MB/s) - ‘heads-talos-2_server-v0.2.0-1377-gd8f6b08-zImage.bundled’ saved [12300632/12300632]

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heads-talos-2_serve 100%[===================>]  56.00K  --.-KB/s    in 0.08s   

2023-03-30 13:30:17 (676 KB/s) - ‘heads-talos-2_server-v0.2.0-1377-gd8f6b08.bootblock’ saved [57348/57348]

--2023-03-30 13:30:17--  https://output.circle-artifacts.com/output/job/2e643375-fb95-492b-8a39-9e80d4df56cc/artifacts/0/build/ppc64/talos-2_server/heads-talos-2_server-v0.2.0-1377-gd8f6b08.rom
Connecting to output.circle-artifacts.com (output.circle-artifacts.com)|18.67.39.93|:443... connected.
HTTP request sent, awaiting response... 302 Found
Location: https://circleci-tasks-prod.s3.us-east-1.amazonaws.com/storage/artifacts/5dcccbcc-64aa-4003-9447-73c37f481c09/2e643375-fb95-492b-8a39-9e80d4df56cc/0/build/ppc64/talos-2_server/heads-talos-2_server-v0.2.0-1377-gd8f6b08.rom?X-Amz-Algorithm=AWS4-HMAC-SHA256&X-Amz-Credential=ASIAQVFQINEONZC5LUUM%2F20230330%2Fus-east-1%2Fs3%2Faws4_request&X-Amz-Date=20230330T173018Z&X-Amz-Expires=60&X-Amz-Security-Token=IQoJb3JpZ2luX2VjEKL%2F%2F%2F%2F%2F%2F%2F%2F%2F%2FwEaCXVzLWVhc3QtMSJGMEQCIEAjwkHBuEgKUbEGwnMnnwxsy4gVYLUl7WjHUObYX088AiBkw0%2FPMJDJER2XYUaah3rSgQjNaL36mMlcTyVgtUl9CCqrAgh7EAMaDDA0NTQ2NjgwNjU1NiIMUpBtPZH22ratQLqQKogClsbwqA7nXlLM0WYUpl%2BSudjldRc75rqUkVKnrG0PuriuEK%2FguT%2Fo7X1DeNtAntu2jkitJX%2FPLOsyItZcNDu4aWlzJAlPqtKT0707V7MBdGgkly0zzYUv94SMPt0atvhaPOlgqKrNAqvrL61BGgf2keZtZApgP%2Fy5PbfQ2oZWoNvx%2BeySSncEsM6kp%2BuriOYjfM5McZmn2b54qN1EV8NzEMei8%2FTcl7wqzL6UCF365V4Wjcj5cxg7ektbS1KcYvO4t6LAhsMJKqaQ9NTQJovlupyDRi6YBVpayfPJtpzgUNZweQolwGD7vnBwknWSieuMRpugdrjvzcUzZVHkG3%2B%2Fr%2Fe4cqqvVcXzMIyNl6EGOp4BAlw%2FR5dDi40uw%2BT%2BKdTLj7khy1ODt3quV9EfjdKaF6E5josJBucrEkyG7vYbJLE95%2B2sAbg1d2HZ4G3ryxwLVXwTErfxVC0GqD4wOP59SyG%2F7RvomHjeJCeKPtNFie2ScAMIqBOzYK1vbeeZ%2BtVNNQD%2FVJYdrwjAmTv5bxXg%2FdXub31rQnEUBlEAaCfXqw3UMXS7i1FjXSm1l625uhg%3D&X-Amz-SignedHeaders=host&x-id=GetObject&X-Amz-Signature=fa4701f48089517d8000bc2894ac317abb3806fdce6128bc6c2734f6afe77550 [following]
--2023-03-30 13:30:17--  https://circleci-tasks-prod.s3.us-east-1.amazonaws.com/storage/artifacts/5dcccbcc-64aa-4003-9447-73c37f481c09/2e643375-fb95-492b-8a39-9e80d4df56cc/0/build/ppc64/talos-2_server/heads-talos-2_server-v0.2.0-1377-gd8f6b08.rom?X-Amz-Algorithm=AWS4-HMAC-SHA256&X-Amz-Credential=ASIAQVFQINEONZC5LUUM%2F20230330%2Fus-east-1%2Fs3%2Faws4_request&X-Amz-Date=20230330T173018Z&X-Amz-Expires=60&X-Amz-Security-Token=IQoJb3JpZ2luX2VjEKL%2F%2F%2F%2F%2F%2F%2F%2F%2F%2FwEaCXVzLWVhc3QtMSJGMEQCIEAjwkHBuEgKUbEGwnMnnwxsy4gVYLUl7WjHUObYX088AiBkw0%2FPMJDJER2XYUaah3rSgQjNaL36mMlcTyVgtUl9CCqrAgh7EAMaDDA0NTQ2NjgwNjU1NiIMUpBtPZH22ratQLqQKogClsbwqA7nXlLM0WYUpl%2BSudjldRc75rqUkVKnrG0PuriuEK%2FguT%2Fo7X1DeNtAntu2jkitJX%2FPLOsyItZcNDu4aWlzJAlPqtKT0707V7MBdGgkly0zzYUv94SMPt0atvhaPOlgqKrNAqvrL61BGgf2keZtZApgP%2Fy5PbfQ2oZWoNvx%2BeySSncEsM6kp%2BuriOYjfM5McZmn2b54qN1EV8NzEMei8%2FTcl7wqzL6UCF365V4Wjcj5cxg7ektbS1KcYvO4t6LAhsMJKqaQ9NTQJovlupyDRi6YBVpayfPJtpzgUNZweQolwGD7vnBwknWSieuMRpugdrjvzcUzZVHkG3%2B%2Fr%2Fe4cqqvVcXzMIyNl6EGOp4BAlw%2FR5dDi40uw%2BT%2BKdTLj7khy1ODt3quV9EfjdKaF6E5josJBucrEkyG7vYbJLE95%2B2sAbg1d2HZ4G3ryxwLVXwTErfxVC0GqD4wOP59SyG%2F7RvomHjeJCeKPtNFie2ScAMIqBOzYK1vbeeZ%2BtVNNQD%2FVJYdrwjAmTv5bxXg%2FdXub31rQnEUBlEAaCfXqw3UMXS7i1FjXSm1l625uhg%3D&X-Amz-SignedHeaders=host&x-id=GetObject&X-Amz-Signature=fa4701f48089517d8000bc2894ac317abb3806fdce6128bc6c2734f6afe77550
Connecting to circleci-tasks-prod.s3.us-east-1.amazonaws.com (circleci-tasks-prod.s3.us-east-1.amazonaws.com)|52.217.43.184|:443... connected.
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Length: 1184256 (1.1M) [application/octet-stream]
Saving to: ‘heads-talos-2_server-v0.2.0-1377-gd8f6b08.rom’

heads-talos-2_serve 100%[===================>]   1.13M  1.60MB/s    in 0.7s    

2023-03-30 13:30:19 (1.60 MB/s) - ‘heads-talos-2_server-v0.2.0-1377-gd8f6b08.rom’ saved [1184256/1184256]

FINISHED --2023-03-30 13:30:19--
Total wall clock time: 7.9s
Downloaded: 3 files, 13M in 5.2s (2.46 MB/s)
user@talos-tests:~/QubesIncoming/heads-tests$ rsync -ravczz --inplace --delete /home/user/QubesIncoming/heads-tests [email protected]:/tmp/images/
sending incremental file list
heads-tests/
heads-tests/heads-talos-2_server-v0.2.0-1377-gd8f6b08-zImage.bundled
heads-tests/heads-talos-2_server-v0.2.0-1377-gd8f6b08.bootblock
heads-tests/heads-talos-2_server-v0.2.0-1377-gd8f6b08.rom

sent 12,812,571 bytes  received 77 bytes  1,507,370.35 bytes/sec
total size is 13,542,236  speedup is 1.06
user@talos-tests:~/QubesIncoming/heads-tests$ ssh -t -l root talos 'cd /tmp/images/heads-tests/ && pflash -r /tmp/talos.pnor && pflash  -F ../../talos.pnor -f -P HBB -p *bootblock* && pflash  -F ../../talos.pnor -f -P HBI -p *.rom* && pflash  -F ../../talos.pnor -f -P BOOTKERNEL -p *zImage.bundled* && mboxctl --backend file:/tmp/talos.pnor && echo "ALL GOOD! Booting and attaching BMC console" && obmcutil poweron && obmc-console-client'
Reading to "/tmp/talos.pnor" from 0x00000000..0x04000000 !
[==================================================] 100% ETA:0s     
About to program "heads-talos-2_server-v0.2.0-1377-gd8f6b08.bootblock" at 0x00205000..0x00213004 !
Programming & Verifying...
[==================================================] 100%
Updating actual size in partition header...
About to program "heads-talos-2_server-v0.2.0-1377-gd8f6b08.rom" at 0x00425000..0x00546200 !
Programming & Verifying...
[==================================================] 100%
Updating actual size in partition header...
About to program "heads-talos-2_server-v0.2.0-1377-gd8f6b08-zImage.bundled" at 0x022a1000..0x02e5c158 !
Programming & Verifying...
[==================================================] 100%
Updating actual size in partition header...
Failed to post message: Connection timed out
Connection to talos closed.
user@talos-tests:~/QubesIncoming/heads-tests$ ssh -t root@talos "obmcutil poweron && obmc-console-client"


--== Welcome to Hostboot hostboot-a2ddbf3/hbicore.bin ==--

Hmmm. Will check things out, bmc in weird state cannot change backend it seems...

@tlaurion
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root@talos:~# mboxctl --lpc-state
LPC Bus Maps: BMC Memory

Wait what?

@krystian-hebel
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krystian-hebel commented Mar 30, 2023

I've seen something like this, noted in comment. Do mboxctl --backend file:... again until it reports success, it should fix it. That connection timed out error shows relatively often, like 10-20% of times.

@tlaurion
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Better

user@talos-tests:~/QubesIncoming/heads-tests$ ssh -t -l root talos 'cd /tmp/images/heads-tests/ && pflash -r /tmp/talos.pnor && pflash  -F ../../talos.pnor -f -P HBB -p *bootblock* && pflash  -F ../../talos.pnor -f -P HBI -p *.rom* && pflash  -F ../../talos.pnor -f -P BOOTKERNEL -p *zImage.bundled* && mboxctl --backend file:/tmp/talos.pnor && echo "ALL GOOD! Booting and attaching BMC console" && obmcutil poweron && obmc-console-client'
Reading to "/tmp/talos.pnor" from 0x00000000..0x04000000 !
[==================================================] 100% ETA:0s     
About to program "heads-talos-2_server-v0.2.0-1377-gd8f6b08.bootblock" at 0x00205000..0x00213004 !
Programming & Verifying...
[==================================================] 100%
Updating actual size in partition header...
About to program "heads-talos-2_server-v0.2.0-1377-gd8f6b08.rom" at 0x00425000..0x00546200 !
Programming & Verifying...
[==================================================] 100%
Updating actual size in partition header...
About to program "heads-talos-2_server-v0.2.0-1377-gd8f6b08-zImage.bundled" at 0x022a1000..0x02e5c158 !
Programming & Verifying...
[==================================================] 100%
Updating actual size in partition header...
SetBackend: Success
ALL GOOD! Booting and attaching BMC console
st type

[NOTE ]  coreboot--TIMELESS--LESSTIME--Heads-v0.2.0-1377-gd8f6b08 Thu Jan  1 00:00:00 UTC 1970 bootblock starting (log level: 7)...
[DEBUG]  FFS header at 0x80060300ffff7000
[DEBUG]  PNOR base at 0x80060300fc000000
[DEBUG]  HBI partition has ECC
[DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x20000.
[DEBUG]  FMAP: base = 0x0 size = 0x100000 #areas = 4
[DEBUG]  FMAP: area COREBOOT found @ 20200 (916992 bytes)
[INFO ]  CBFS: mcache @0xf8231000 built for 10 files, used 0x1f0 of 0x2000 bytes
[INFO ]  CBFS: Found 'fallback/romstage' @0x80 size 0x13dbb in mcache @0xf823102c
[INFO ]  TPM LOG: clearing the log
[DEBUG]  FMAP: area FMAP found @ 20000 (512 bytes)
[DEBUG]  TPM: Digest of `FMAP: FMAP` to PCR 2 logged
[DEBUG]  FMAP: area BOOTBLOCK found @ 0 (131072 bytes)
[DEBUG]  TPM: Digest of `FMAP: BOOTBLOCK` to PCR 2 logged
[DEBUG]  CRTM initialized.
[DEBUG]  TPM: Digest of `CBFS: fallback/romstage` to PCR 2 logged
[DEBUG]  BS: bootblock times (exec / console): total (unknown) / 4 ms


[NOTE ]  coreboot--TIMELESS--LESSTIME--Heads-v0.2.0-1377-gd8f6b08 Thu Jan  1 00:00:00 UTC 1970 romstage starting (log level: 7)...
[DEBUG]  IPMI: romstage PNP BT 0xe4
[INFO ]  Get BMC self test result...Function Not Implemented
[INFO ]  Initializing IPMI BMC watchdog timer
[INFO ]  IPMI BMC watchdog initialized and started.
[DEBUG]  Initializing FSI...
[DEBUG]  Initialized FSI (chips mask: 0x01)
[NOTE ]  Building MVPDs...
[INFO ]  starting istep 8.1
[INFO ]  starting istep 8.2
[INFO ]  starting istep 8.3
[INFO ]  starting istep 8.4
[INFO ]  starting istep 8.9
[DEBUG]  Base epsilon values read from table:
[DEBUG]   R_T[0] = 22
[DEBUG]   R_T[1] = 22
[DEBUG]   R_T[2] = 103
[DEBUG]   W_T[0] = 5
[DEBUG]   W_T[1] = 33
[DEBUG]  Scaled epsilon values based on +20 percent guardband:
[DEBUG]   R_T[0] = 27
[DEBUG]   R_T[1] = 27
[DEBUG]   R_T[2] = 124
[DEBUG]   W_T[0] = 6
[DEBUG]   W_T[1] = 40
[INFO ]  starting istep 8.10
[INFO ]  starting istep 8.11
[INFO ]  starting istep 9.2
[INFO ]  starting istep 9.4
[INFO ]  starting istep 9.6
[INFO ]  starting istep 9.7
[INFO ]  starting istep 10.1
[INFO ]  starting istep 10.6
[INFO ]  starting istep 10.10
[INFO ]  starting istep 10.12
[INFO ]  starting istep 10.13
[DEBUG]  FFS header at 0x80060300ffff7000
[DEBUG]  PNOR base at 0x80060300fc000000
[DEBUG]  MEMD partition has ECC
[INFO ]  I2C transfer failed to complete (0x04011f0104000000)
[INFO ]  No memory DIMM at address 51
[INFO ]  I2C transfer failed to complete (0x04011f0104000000)
[INFO ]  No memory DIMM at address 52
[INFO ]  I2C transfer failed to complete (0x04011f0104000000)
[INFO ]  No memory DIMM at address 53
[INFO ]  I2C transfer failed to complete (0x04011f0104000000)
[INFO ]  No memory DIMM at address D4
[INFO ]  I2C transfer failed to complete (0x04011f0104000000)
[INFO ]  No memory DIMM at address D5
[INFO ]  I2C transfer failed to complete (0x04011f0104000000)
[INFO ]  No memory DIMM at address D6
[INFO ]  I2C transfer failed to complete (0x04011f0104000000)
[INFO ]  No memory DIMM at address D7
[DEBUG]  SPD @ 0x50
[INFO ]  SPD: module type is DDR4
[INFO ]  SPD: module part number is M393A1K43BB0-CRC    
[INFO ]  SPD: banks 16, ranks 1, rows 16, columns 10, density 8192 Mb
[INFO ]  SPD: device width 8 bits, bus width 64 bits
[INFO ]  SPD: module size is 8192 MB (per channel)
[INFO ]  starting istep 13.1
[INFO ]  starting istep 13.2
[INFO ]  starting istep 13.3
[INFO ]  starting istep 13.4
[INFO ]  starting istep 13.5
[INFO ]  starting istep 13.6
[INFO ]  starting istep 13.7
[INFO ]  starting istep 13.8
[INFO ]  starting istep 13.9
[INFO ]  starting istep 13.10
[DEBUG]  CCS took 2 us (3 us timeout), 1 instruction(s)
[DEBUG]  CCS took 2 us (2 us timeout), 14 instruction(s)
[DEBUG]  RCD dump for I2C address 0x58:
[DEBUG]  0xf820fa40: 80 b3 40 42 30 00 00 00 02 01 00 03 cb e3 c0 0d  ..@B0...........
[DEBUG]  0xf820fa50: 00 00 39 00 00 00 00 00 00 00 07 00 00 00 00 00  ..9.............
[INFO ]  starting istep 13.11
[DEBUG]  CCS took 2 us (7 us timeout), 2 instruction(s)
[DEBUG]  Write Leveling starting
[DEBUG]  CCS took 12 us (92 us timeout), 5 instruction(s)
[DEBUG]  Write Leveling done
[DEBUG]  Initial Pattern Write starting
[DEBUG]  CCS took 5 us (38 us timeout), 5 instruction(s)
[DEBUG]  Initial Pattern Write done
[DEBUG]  DQS alignment starting
[DEBUG]  CCS took 9 us (44 us timeout), 1 instruction(s)
[DEBUG]  DQS alignment done
[DEBUG]  Read Clock Alignment starting
[DEBUG]  CCS took 8 us (82 us timeout), 1 instruction(s)
[DEBUG]  Read Clock Alignment done
[DEBUG]  Read Centering starting
[DEBUG]  CCS took 37 us (120 us timeout), 1 instruction(s)
[DEBUG]  Read Centering done
[DEBUG]  Write Centering starting
[DEBUG]  CCS took 7544 us (11314 us timeout), 7 instruction(s)
[DEBUG]  Write Centering done
[DEBUG]  Coarse write/read starting
[DEBUG]  CCS took 5 us (24 us timeout), 1 instruction(s)
[DEBUG]  Coarse write/read done
[INFO ]  starting istep 13.12
[INFO ]  starting istep 13.13
[INFO ]  starting istep 14.1
[INFO ]  starting istep 14.2
[INFO ]  starting istep 14.3
[INFO ]  Initializing PEC0...
[INFO ]  Initializing PEC1...
[INFO ]  Initializing PEC2...
[INFO ]  Initializing PHB0...
[INFO ]  Initializing PHB1...
[INFO ]  Initializing PHB2...
[INFO ]  Initializing PHB3...
[INFO ]  Initializing PHB4...
[INFO ]  Initializing PHB5...
[INFO ]  starting istep 14.4
[INFO ]  starting istep 14.5
[WARN ]  0xF000F = 221d104900008040
[DEBUG]  CBMEM:
[DEBUG]  IMD: root @ 0xffeff000 254 entries.
[DEBUG]  IMD: root @ 0xffefec00 62 entries.
[DEBUG]  FMAP: area COREBOOT found @ 20200 (916992 bytes)
[DEBUG]  FFS header at 0x80060300ffff7000
[DEBUG]  PNOR base at 0x80060300fc000000
[DEBUG]  HBI partition has ECC
[INFO ]  CBFS: Found 'fallback/ramstage' @0x13ec0 size 0xeeeb in mcache @0xf8231080
[DEBUG]  TPM: Digest of `CBFS: fallback/ramstage` to PCR 2 logged
[DEBUG]  BS: romstage times (exec / console): total (unknown) / 24 ms


[NOTE ]  coreboot--TIMELESS--LESSTIME--Heads-v0.2.0-1377-gd8f6b08 Thu Jan  1 00:00:00 UTC 1970 ramstage starting (log level: 7)...
[INFO ]  Enumerating buses...
[DEBUG]  Root Device scanning...
[DEBUG]  DD21, boot core: 18
[DEBUG]  FFS header at 0x80060300ffff7000
[DEBUG]  PNOR base at 0x80060300fc000000
[DEBUG]  HCODE partition has ECC
[DEBUG]  FFS header at 0x80060300ffff7000
[DEBUG]  PNOR base at 0x80060300fc000000
[DEBUG]  OCC partition has ECC
[DEBUG]  Base epsilon values read from table:
[DEBUG]   R_T[0] = 22
[DEBUG]   R_T[1] = 22
[DEBUG]   R_T[2] = 103
[DEBUG]   W_T[0] = 5
[DEBUG]   W_T[1] = 33
[DEBUG]  Scaled epsilon values based on +20 percent guardband:
[DEBUG]   R_T[0] = 27
[DEBUG]   R_T[1] = 27
[DEBUG]   R_T[2] = 124
[DEBUG]   W_T[0] = 6
[DEBUG]   W_T[1] = 40
[DEBUG]  FFS header at 0x80060300ffff7000
[DEBUG]  PNOR base at 0x80060300fc000000
[DEBUG]  WOFDATA partition has ECC
[NOTE ]  Matching WOF tables section not found, disabling WOF
[DEBUG]  Safe mode freq = 1833412 kHZ, voltage = 711 mv
[INFO ]  starting istep 15.2
[INFO ]  starting istep 15.3
[INFO ]  starting istep 15.4
[DEBUG]  Starting PM complex...
[DEBUG]  Attempting PGPE activation...
[DEBUG]  PGPE was activated successfully
[DEBUG]  Done starting PM complex
[INFO ]  starting istep 16.1
[DEBUG]  XIVE configured, entering dead man loop
[EMERG]  ASSERTION ERROR: file '(filenames not available on timeless builds)', line 404
[INFO ]  starting istep 18.11
[INFO ]  starting istep 18.12
[DEBUG]  Activating OCC...
[DEBUG]  Done activating OCC
[DEBUG]  CPU_CLUSTER: 0 enabled
[DEBUG]  PNP: 00e4.0 enabled
[DEBUG]  scan_bus: bus Root Device finished in 2507 msecs
[INFO ]  done
[DEBUG]  BS: BS_DEV_ENUMERATE run times (exec / console): 2501 / 8 ms
[INFO ]  Allocating resources...
[INFO ]  Reading resources...
[ERROR]  CPU_CLUSTER: 0 missing read_resources
[INFO ]  Done reading resources.
[ERROR]  CPU_CLUSTER: 0 missing set_resources
[DEBUG]  PNP: 00e4.0 00 <- [0x00000000000000e4 - 0x00000000000000e6] size 0x00000003 gran 0x00 io
[INFO ]  Done setting resources.
[INFO ]  Done allocating resources.
[DEBUG]  BS: BS_DEV_RESOURCES run times (exec / console): 1 / 2 ms
[INFO ]  Enabling resources...
[INFO ]  done.
[INFO ]  tpm_vendor_probe: ValidSts bit set(1) in TPM_ACCESS register after 0 ms
[DEBUG]  I2C TPM 2:20 (chip type slb9645tt device-id 0xD115)
[DEBUG]  TPM: Startup
[DEBUG]  TPM: command 0x99 returned 0x0
[DEBUG]  TPM: Asserting physical presence
[DEBUG]  TPM: command 0x4000000a returned 0x0
[DEBUG]  TPM: command 0x65 returned 0x0
[DEBUG]  TPM: flags disable=0, deactivated=0, nvlocked=0
[DEBUG]  TPM: Write digests cached in TPM log to PCR
[DEBUG]  TPM: Write digest for FMAP: FMAP into PCR 2
[DEBUG]  TPM: command 0x14 returned 0x0
[DEBUG]  TPM: Write digest for FMAP: BOOTBLOCK into PCR 2
[DEBUG]  TPM: command 0x14 returned 0x0
[DEBUG]  TPM: Write digest for CBFS: fallback/romstage into PCR 2
[DEBUG]  TPM: command 0x14 returned 0x0
[DEBUG]  TPM: Write digest for CBFS: fallback/ramstage into PCR 2
[DEBUG]  TPM: command 0x14 returned 0x0
[INFO ]  TPM: setup succeeded
[DEBUG]  BS: BS_DEV_INIT entry times (exec / console): 84 / 6 ms
[INFO ]  Initializing devices...
[DEBUG]  PNP: 00e4.0 init
[DEBUG]  IPMI: PNP BT 0xe4
[INFO ]  Get BMC self test result...Function Not Implemented
[INFO ]  IPMI: Found man_id 0x6cb0000, prod_id 0x1000000
[INFO ]  IPMI: Version 2.0
[DEBUG]  PNP: 00e4.0 init finished in 21 msecs
[INFO ]  Devices initialized
[DEBUG]  BS: BS_DEV_INIT run times (exec / console): 21 / 2 ms
[INFO ]  Finalize devices...
[INFO ]  Devices finalized
[DEBUG]  Writing coreboot table at 0xffed7000
[DEBUG]   0. 0000000000000000-00000000f8207fff: RAM
[DEBUG]   1. 00000000f8208000-00000000f820ffff: RAMSTAGE
[DEBUG]   2. 00000000f8210000-00000000f8ffffff: RAM
[DEBUG]   3. 00000000f9000000-00000000f92a1fff: RAMSTAGE
[DEBUG]   4. 00000000f92a2000-00000000ffed6fff: RAM
[DEBUG]   5. 00000000ffed7000-00000000ffefffff: CONFIGURATION TABLES
[DEBUG]   6. 00000000fff00000-00000001ff3fffff: RAM
[DEBUG]   7. 00000001ff400000-00000001ffffffff: RESERVED
[DEBUG]  FMAP: area COREBOOT found @ 20200 (916992 bytes)
[DEBUG]  FFS header at 0x80060300ffff7000
[DEBUG]  PNOR base at 0x80060300fc000000
[DEBUG]  HBI partition has ECC
[DEBUG]  Wrote coreboot table at: 0xffed7000, 0x240 bytes, checksum bfaf0000
[DEBUG]  coreboot table: 600 bytes.
[DEBUG]  IMD ROOT    0. 0xffeff000 0x00001000
[DEBUG]  IMD SMALL   1. 0xffefe000 0x00001000
[DEBUG]  CONSOLE     2. 0xffede000 0x00020000
[DEBUG]  TPM2 TCGLOG 3. 0xffedc000 0x00001180
[DEBUG]  MEM INFO    4. 0xffed9000 0x000022b0
[DEBUG]  COREBOOT    5. 0xffed7000 0x00002000
[DEBUG]  IMD small region:
[DEBUG]    IMD ROOT    0. 0xffefec00 0x00000400
[DEBUG]    RO MCACHE   1. 0xffefea00 0x000001f0
[DEBUG]    FMAP        2. 0xffefe920 0x000000e0
[DEBUG]  BS: BS_WRITE_TABLES run times (exec / console): 0 / 8 ms
[INFO ]  CBFS: Found 'fallback/payload' @0x29440 size 0x63392 in mcache @0xffefeb84
[DEBUG]  TPM: Extending digest for `CBFS: fallback/payload` into PCR 2
[DEBUG]  TPM: command 0x14 returned 0x0
[DEBUG]  TPM: Digest of `CBFS: fallback/payload` to PCR 2 measured
[DEBUG]  Checking segment from ROM address 0xf8380000
[DEBUG]  Checking segment from ROM address 0xf838001c
[DEBUG]  Checking segment from ROM address 0xf8380038
[DEBUG]  Loading segment from ROM address 0xf8380000
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x00000000 memsize 0x173c00 srcaddr 0xf8380054 filesize 0x6333e
[DEBUG]  Loading Segment: addr: 0x00000000 memsz: 0x0000000000173c00 filesz: 0x000000000006333e
[DEBUG]  using LZMA
[DEBUG]  Loading segment from ROM address 0xf838001c
[DEBUG]    BSS 0x00300000 (113776 byte)
[DEBUG]  Loading Segment: addr: 0x00300000 memsz: 0x000000000001bc70 filesz: 0x0000000000000000
[DEBUG]  it's not compressed!
[DEBUG]  Clearing Segment: addr: 0x0000000000300000 memsz: 0x000000000001bc70
[DEBUG]  Loading segment from ROM address 0xf8380038
[DEBUG]    Entry Point 0x00002570
[DEBUG]  BS: BS_PAYLOAD_LOAD run times (exec / console): 440 / 7 ms
[INFO ]  coreboot TPM 2.0 measurements:

[INFO ]   PCR-2 27c4f1fa214480c8626397a15981ef3a9323717f SHA1 [FMAP: FMAP]
[INFO ]   PCR-2 baacf990e0e2206c3e03483a4638d876bba5614f SHA1 [FMAP: BOOTBLOCK]
[INFO ]   PCR-2 1627520c969bba0e08bf0a316327ec07cef534a2 SHA1 [CBFS: fallback/romstage]
[INFO ]   PCR-2 cb4220b537a06b89d082416f688a0c91dae02470 SHA1 [CBFS: fallback/ramstage]
[INFO ]   PCR-2 a0db7074b182bd4697e29599dbc3f6c3a807c8e4 SHA1 [CBFS: fallback/payload]

[DEBUG]  BS: BS_PAYLOAD_BOOT entry times (exec / console): 0 / 3 ms
[DEBUG]  Jumping to boot code at 0x00002570(0xffed7000)
[INFO ]  CBFS: Found '1-cpu.dtb' @0x23380 size 0x24e7 in mcache @0xffefeb3c
[DEBUG]  TPM: Extending digest for `CBFS: 1-cpu.dtb` into PCR 2
[DEBUG]  TPM: command 0x14 returned 0x0
[DEBUG]  TPM: Digest of `CBFS: 1-cpu.dtb` to PCR 2 measure[    2.165270863,5] OPAL v6.3-rc2-32-gfa060c2c starting...
[    2.165274374,7] initial console log level: memory 7, driver 5
[    2.165276296,6] CPU: P9 generation processor (max 4 threads/core)
[    2.165278041,7] CPU: Boot CPU PIR is 0x004c PVR is 0x004e1201
[    2.165280534,7] OPAL table: 0x30108230 .. 0x30108810, branch table: 0x30002000
[    2.165283524,7] Assigning physical memory map table for nimbus
[    2.165285916,7] FDT: Parsing fdt @0xf90ab138
[    2.165995198,6] CHIP: Initialised chip 0 from xscom@603fc00000000
[    2.166018977,6] P9 DD2.10 detected
[    2.166020401,5] CHIP: Chip ID 0000 type: P9N DD2.10
[    2.166022393,7] XSCOM: Base address: 0x603fc00000000
[    2.166031226,7] XSTOP: XSCOM addr = 0x5012000, FIR bit = 31
[    2.166033365,6] MFSI 0:0: Initialized
[    2.166034754,6] MFSI 0:2: Initialized
[    2.166036164,6] MFSI 0:1: Initialized
[    2.166089861,6] LPC: LPC[000]: Initialized
[    2.166091250,7] LPC: access via MMIO @0x6030000000000
[    2.166104267,7] LPC: Default bus on chip 0x0
[    2.166111053,7] CPU: New max PIR set to 0x57
[    2.166141570,6] MEM: parsing reserved memory from node /reserved-memory
[    2.166145839,7] HOMER: Init chip 0
[    2.166147871,7]   PBA BAR0 : 0x00000001ff400000
[    2.166149510,7]   PBA MASK0: 0x0000000000300000
[    2.166151172,7]   HOMER Image at 0x1ff400000 size 4MB
[    2.166153825,7]   PBA BAR2 : 0x00000001ff800000
[    2.166155462,7]   PBA MASK2: 0x0000000000700000
[    2.166157054,7]   OCC Common Area at 0x1ff800000 size 8MB
[    2.166159323,7] CPU: decrementer bits 56
[    2.166163847,6] CPU: CPU from DT PIR=0x0048 Server#=0x48 State=3
[    2.166169552,6] CPU:  4 secondary threads
[    2.166172654,6] CPU: CPU from DT PIR=0x004c Server#=0x4c State=3
[    2.166177835,6] CPU:  4 secondary threads
[    2.166180827,6] CPU: CPU from DT PIR=0x0050 Server#=0x50 State=3
[    2.166186304,6] CPU:  4 secondary threads
[    2.166189300,6] CPU: CPU from DT PIR=0x0054 Server#=0x54 State=3
[    2.166194677,6] CPU:  4 secondary threads
[    2.166242261,6] PLAT: AST SIO unavailable!
[    2.166254690,7] UART: Using LPC IRQ 4
[    2.168297033,5] PLAT: Detected Talos platform
[    2.168338336,5] PLAT: Detected BMC platform ast2500:openbmc
[    2.183289040,5] CPU: All 16 processors called in...
[   11.285247681,7] LPC: Routing irq 10, policy: 0 (r=1)
[   11.285248872,7] LPC: SerIRQ 10 using route 0 targetted at OPAL
[   12.290553774,5] HIOMAP: Negotiated hiomap protocol v2
[   12.290613220,5] HIOMAP: Block size is 4KiB
[   12.290646583,5] HIOMAP: BMC suggested flash timeout of 8s
[   12.290697001,5] HIOMAP: Flash size is 64MiB
[   12.290734337,5] HIOMAP: Erase granule size is 4KiB
[   15.505461507,5] FLASH: Found system flash: (unnamed) id:0
[   16.296183274,3] STB: hw-key-hash not found
[   16.296245342,3] STB: hw_key-hash wrong size 0 (expected=64)
[   16.296317689,5] STB: Found tpm0,i2c_tpm_infineon evLogLen=608 evLogSize=4480
[   16.296383729,7] LPC: Routing irq 4, policy: 0 (r=1)
[   16.296384736,7] LPC: SerIRQ 4 using route 1 targetted at OPAL
[   16.296509005,5] OCC: All Chip Rdy after 0 ms
[   17.093743815,3] STB: VERSION NOT VERIFIED, invalid param. buf=0x30601188, len=4326 key-hash=0x0 hash-size=64
[   17.093854221,5] STB: VERSION hash calculated
[   17.178995988,5] STB: VERSION measured on pcr3 (tpm0, evType 0x5, evLogLen 687)
[   18.214892662,3] STB: IMA_CATALOG NOT VERIFIED, invalid param. buf=0x30603218, len=73728 key-hash=0x0 hash-size=64
[   18.215198649,5] STB: IMA_CATALOG hash calculated
[   18.268519959,3] I2C: Transfer error occurred
[   18.268581357,3] I2C: Chip 00000000 Eng. 2 Port 0--
 xscom_base=0x00000000000a2000	state=2	bytes_sent=0
[   18.268706734,3] I2C: Request info--
 addr=0x0020	offset_bytes=1	offset=2	len=3
[   18.268757995,3] I2C:  start_time=0000000235521056 end_time=0000000235524956 (duration=0000000000003900)
[   18.268841261,3] I2C: Register dump--
    cmd:0xc140000109000000	mode:0x0048000009000000	stat:0x0901080009000000
  estat:0x0800991809000000	intm:0x0000000009000000	intc:0x0000092909000000
[   18.269000309,3] I2C: Error bits set: arbitration loss, 
[   18.295756240,5] STB: IMA_CATALOG measured on pcr2 (tpm0, evType 0x5, evLogLen 770)
[   18.411338952,3] CAPP: Error loading ucode lid. index=201d1

@tlaurion
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@tlaurion could you test https://app.circleci.com/pipelines/github/Dasharo/heads/11/workflows/5d083562-57ae-4095-8c5c-b46b6cca4f8f/jobs/309/artifacts? Things to check:

* `cbmem -L` works

* `cbmem -L` shows ~17 entries (instead of 6)

* fans are quiet
  • cbmem -L
~ # cbmem -L
TPM2 log:
	Specification: 2.00
	Platform class: PC Client
TPM2 log entry 1:
	PCR: 2
	Event type: Action
	Digests:
		 SHA1: 27c4f1fa214480c8626397a15981ef3a9323717f
	Event data: 50 FMAP: FMAP
TPM2 log entry 2:
	PCR: 2
	Event type: Action
	Digests:
		 SHA1: baacf990e0e2206c3e03483a4638d876bba5614f
	Event data: 50 FMAP: BOOTBLOCK
TPM2 log entry 3:
	PCR: 2
	Event type: Action
	Digests:
		 SHA1: 1627520c969bba0e08bf0a316327ec07cef534a2
	Event data: 50 CBFS: fallback/romstage
TPM2 log entry 4:
	PCR: 2
	Event type: Action
	Digests:
		 SHA1: cb4220b537a06b89d082416f688a0c91dae02470
	Event data: 50 CBFS: fallback/ramstage
TPM2 log entry 5:
	PCR: 2
	Event type: Action
	Digests:
		 SHA1: a0db7074b182bd4697e29599dbc3f6c3a807c8e4
	Event data: 50 CBFS: fallback/payload
TPM2 log entry 6:
	PCR: 2
	Event type: Action
	Digests:
		 SHA1: 47b49026133377e05193f8440c9a7cad239e883c
	Event data: 50 CBFS: 1-cpu.dtb
TPM2 log entry 7:
	PCR: 3
	Event type: Action
	Digests:
		 SHA256: 6e7b06693452d997ac534e823b1ea79e5bb8ed19ba8a7af878abf10199c3d515
		 SHA1: 6e7b06693452d997ac534e823b1ea79e5bb8ed19
	Event data: 7 VERSION
TPM2 log entry 8:
	PCR: 2
	Event type: Action
	Digests:
		 SHA256: de73053377e1ae5ba5d2b637a4f5bfaeb410137722f11ef135e7a1be524e3092
		 SHA1: de73053377e1ae5ba5d2b637a4f5bfaeb4101377
	Event data: 11 IMA_CATALOG
TPM2 log entry 9:
	PCR: 4
	Event type: Action
	Digests:
		 SHA256: 3c96e13178b3c1e93a1ece4471e273295d7e9e990b8748d0155db2071dceecfb
		 SHA1: 3c96e13178b3c1e93a1ece4471e273295d7e9e99
	Event data: 10 BOOTKERNEL
TPM2 log entry 10:
	PCR: 0
	Event type: Separator
	Digests:
		 SHA256: ad95131bc0b799c0b1af477fb14fcf26a6a9f76079e48bf090acb7e8367bfd0e
		 SHA1: d9be6524a5f5047db5866813acf3277892a7a30a
	Event data: 4 ����
TPM2 log entry 11:
	PCR: 1
	Event type: Separator
	Digests:
		 SHA256: ad95131bc0b799c0b1af477fb14fcf26a6a9f76079e48bf090acb7e8367bfd0e
		 SHA1: d9be6524a5f5047db5866813acf3277892a7a30a
	Event data: 4 ����
TPM2 log entry 12:
	PCR: 2
	Event type: Separator
	Digests:
		 SHA256: ad95131bc0b799c0b1af477fb14fcf26a6a9f76079e48bf090acb7e8367bfd0e
		 SHA1: d9be6524a5f5047db5866813acf3277892a7a30a
	Event data: 4 ����
TPM2 log entry 13:
	PCR: 3
	Event type: Separator
	Digests:
		 SHA256: ad95131bc0b799c0b1af477fb14fcf26a6a9f76079e48bf090acb7e8367bfd0e
		 SHA1: d9be6524a5f5047db5866813acf3277892a7a30a
	Event data: 4 ����
TPM2 log entry 14:
	PCR: 4
	Event type: Separator
	Digests:
		 SHA256: ad95131bc0b799c0b1af477fb14fcf26a6a9f76079e48bf090acb7e8367bfd0e
		 SHA1: d9be6524a5f5047db5866813acf3277892a7a30a
	Event data: 4 ����
TPM2 log entry 15:
	PCR: 5
	Event type: Separator
	Digests:
		 SHA256: ad95131bc0b799c0b1af477fb14fcf26a6a9f76079e48bf090acb7e8367bfd0e
		 SHA1: d9be6524a5f5047db5866813acf3277892a7a30a
	Event data: 4 ����
TPM2 log entry 16:
	PCR: 6
	Event type: Separator
	Digests:
		 SHA256: ad95131bc0b799c0b1af477fb14fcf26a6a9f76079e48bf090acb7e8367bfd0e
		 SHA1: d9be6524a5f5047db5866813acf3277892a7a30a
	Event data: 4 ����
TPM2 log entry 17:
	PCR: 7
	Event type: Separator
	Digests:
		 SHA256: ad95131bc0b799c0b1af477fb14fcf26a6a9f76079e48bf090acb7e8367bfd0e
		 SHA1: d9be6524a5f5047db5866813acf3277892a7a30a
	Event data: 4 ����
  • Fans are quiet: yes

@tlaurion
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tlaurion commented Mar 30, 2023

~ # ls /dev/nvme*

@krystian-hebel not on my side. :/

@krystian-hebel
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Is the adapter plugged in to CPU1 PCIe ports? Unfortunately most of them belong to CPU2, and I don't think it's clearly marked on the board.

image

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tlaurion commented Mar 30, 2023

Ha! No was connected to lowest and smallesy connector. Will reconnect

@krystian-hebel
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Rebase done, when CI finishes it should be ready for testing. Depending on results it may be identical to final release, +/- hash in revision.

@krystian-hebel krystian-hebel marked this pull request as ready for review March 30, 2023 19:54
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@krystian-hebel nvme drive discovered :)

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tlaurion commented Mar 31, 2023

@krystian-hebel seems like usb hid was lost, so no usb keyboard support under Heads. Will check that

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tlaurion commented Mar 31, 2023

Houla @krystian-hebel

Ok, after manually having followed #1360 to kexec manually debian netinstall and install from network to nvme (success), host rebooted.

It asked to setup new boot device, selected /dev/nvme1p2 (unencrypted boot), reflashed internally, success.
But then on reboot, TPM not detected.
Proceeded to factory reset/reownership:

Resetting GPG Key...
(this will take around 3 minutes...)


Changing default GPG Admin PIN


Changing default GPG User PIN


Reading current firmware...
(this will take a minute or two)


Adding generated key to current firmware and re-flashing...


Signing boot files and generating checksums...

[ 2758.046998364,3] I2C: request timed out!
[ 2758.047094632,3] I2C: Chip 00000000 Eng. 2 Port 0--
 xscom_base=0x00000000000a2000	state=3	bytes_sent=0
[ 2758.047232361,3] I2C: Request info--
 addr=0x0020	offset_bytes=1	offset=1	len=1
[ 2758.047327005,3] I2C:  start_time=00000148ca3fda29 end_time=00000148ca48217a (duration=0000000000084751)
[ 2758.047474268,3] I2C: Register dump--
    cmd:0xd141000100000000	mode:0x0048000000000000	stat:0x0001170000000000
  estat:0x080f5dd800000000	intm:0x0000000000000000	intc:0x0000004600000000
[ 2758.047805756,3] I2C: Error bits set: 
[ 2758.054227295,3] I2C: request timed out!
[ 2758.054309448,3] I2C: Chip 00000000 Eng. 2 Port 0--
 xscom_base=0x00000000000a2000	state=3	bytes_sent=0
[ 2758.054461725,3] I2C: Request info--
 addr=0x0020	offset_bytes=1	offset=1	len=1
[ 2758.054565681,3] I2C:  start_time=00000148caae270b end_time=00000148cab67029 (duration=000000000008491e)
[ 2758.054717277,3] I2C: Register dump--
    cmd:0xd141000100000000	mode:0x0048000000000000	stat:0x0001170000000000
  estat:0x080f5dd800000000	intm:0x0000000000000000	intc:0x0000004600000000
[ 2758.055022899,3] I2C: Error bits set: 
[ 2758.063392970,3] I2C: request timed out!
[ 2758.063444373,3] I2C: Chip 00000000 Eng. 2 Port 0--
 xscom_base=0x00000000000a2000	state=3	bytes_sent=0
[ 2758.063581670,3] I2C: Request info--
 addr=0x0020	offset_bytes=1	offset=1	len=1
[ 2758.063670308,3] I2C:  start_time=00000148cb3a01ff end_time=00000148cb424bc7 (duration=00000000000849c8)
[ 2758.063811568,3] I2C: Register dump--
    cmd:0xd141000100000000	mode:0x0048000000000000	stat:0x0001170000000000
  estat:0x080f5dd800000000	intm:0x0000000000000000	intc:0x0000004600000000
[ 2758.064096973,3] I2C: Error bits set: 
183992617: 000E4522135100000001
[ 2758.110467396,3] I2C: request timed out!
[ 2758.110540387,3] I2C: Chip 00000000 Eng. 2 Port 0--
 xscom_base=0x00000000000a2000	state=3	bytes_sent=0
[ 2758.110682651,3] I2C: Request info--
 addr=0x0020	offset_bytes=1	offset=1	len=1
[ 2758.110786842,3] I2C:  start_time=00000148ce084f98 end_time=00000148ce109805 (duration=000000000008486d)
[ 2758.110927756,3] I2C: Register dump--
    cmd:0xd141000100000000	mode:0x0048000000000000	stat:0x0001170000000000
  estat:0x080f5dd800000000	intm:0x0000000000000000	intc:0x0000004600000000
[ 2758.111177010,3] I2C: Error bits set: 
[ 2758.116941193,3] I2C: request timed out!
[ 2758.117023132,3] I2C: Chip 00000000 Eng. 2 Port 0--
 xscom_base=0x00000000000a2000	state=3	bytes_sent=0
[ 2758.117159942,3] I2C: Request info--
 addr=0x0020	offset_bytes=1	offset=1	len=1
[ 2758.117279177,3] I2C:  start_time=00000148ce6b1825 end_time=00000148ce736075 (duration=0000000000084850)
[ 2758.117420115,3] I2C: Register dump--
    cmd:0xd141000102000000	mode:0x0048000002000000	stat:0x02010c0102000000
  estat:0x0800dd1802000000	intm:0x0000000002000000	intc:0x0000022a02000000
[ 2758.117731410,3] I2C: Error bits set: 
[ 2758.123488842,3] I2C: request timed out!
[ 2758.123555434,3] I2C: Chip 00000000 Eng. 2 Port 0--
 xscom_base=0x00000000000a2000	state=3	bytes_sent=0
[ 2758.123697445,3] I2C: Request info--
 addr=0x0020	offset_bytes=1	offset=1	len=1
[ 2758.123791272,3] I2C:  start_time=00000148cecf0401 end_time=00000148ced74945 (duration=0000000000084544)
[ 2758.123937447,3] I2C: Register dump--
    cmd:0xd141000100000000	mode:0x0048000000000000	stat:0x0001170000000000
  estat:0x080f5dd800000000	intm:0x0000000000000000	intc:0x0000004600000000
[ 2758.124232406,3] I2C: Error bits set: 

Seems like TPM is not solid in this tested commit.


Again, we are talking about reboot under Heads here, which uses sysrq:
https://github.com/osresearch/heads/blob/1617b6ccbaf3f3885416a518e69853f3d7ab06ad/initrd/bin/reboot#L11-L18

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@krystian-hebel

Poweroff
https://github.com/osresearch/heads/blob/1617b6ccbaf3f3885416a518e69853f3d7ab06ad/initrd/bin/poweroff#L11-L18

~ # poweroff
[   90.877063] sysrq: Emergency Sync
[   90.877788] sysrq: Emergency Remount R/O
[   90.878142] sysrq: Power Off
~ # [   91.593217] reboot: Power down
[ 2956.390066178,5] OPAL: Shutdown request type 0x0...

Then
user@talos-tests:~/QubesIncoming/heads-tests$ ssh -t root@talos "obmcutil poweron && obmc-console-client"

st type 0x0

[NOTE ]  coreboot--TIMELESS--LESSTIME--Heads-v0.2.0-1501-g1a69b1d Thu Jan  1 00:00:00 UTC 1970 bootblock starting (log level: 7)...
[DEBUG]  FFS header at 0x80060300ffff7000
[DEBUG]  PNOR base at 0x80060300fc000000
[DEBUG]  HBI partition has ECC
[DEBUG]  FMAP: Found "FLASH" version 1.1 at 0x20000.
[DEBUG]  FMAP: base = 0x0 size = 0x100000 #areas = 4
[DEBUG]  FMAP: area COREBOOT found @ 20200 (916992 bytes)
[INFO ]  CBFS: mcache @0xf8231000 built for 13 files, used 0x298 of 0x2000 bytes
[INFO ]  CBFS: Found 'fallback/romstage' @0x80 size 0x13dbb in mcache @0xf823102c
[INFO ]  TPM LOG: clearing the log
[DEBUG]  FMAP: area FMAP found @ 20000 (512 bytes)
[DEBUG]  TPM: Digest of `FMAP: FMAP` to PCR 2 logged
[DEBUG]  FMAP: area BOOTBLOCK found @ 0 (131072 bytes)
[DEBUG]  TPM: Digest of `FMAP: BOOTBLOCK` to PCR 2 logged
[DEBUG]  CRTM initialized.
[DEBUG]  TPM: Digest of `CBFS: fallback/romstage` to PCR 2 logged
[DEBUG]  BS: bootblock times (exec / console): total (unknown) / 4 ms


[NOTE ]  coreboot--TIMELESS--LESSTIME--Heads-v0.2.0-1501-g1a69b1d Thu Jan  1 00:00:00 UTC 1970 romstage starting (log level: 7)...
[DEBUG]  IPMI: romstage PNP BT 0xe4
[INFO ]  Get BMC self test result...Function Not Implemented
[INFO ]  Initializing IPMI BMC watchdog timer
[INFO ]  IPMI BMC watchdog initialized and started.
[DEBUG]  Initializing FSI...
[DEBUG]  Initialized FSI (chips mask: 0x01)
[NOTE ]  Building MVPDs...
[INFO ]  starting istep 8.1
[INFO ]  starting istep 8.2
[INFO ]  starting istep 8.3
[INFO ]  starting istep 8.4
[INFO ]  starting istep 8.9
[DEBUG]  Base epsilon values read from table:
[DEBUG]   R_T[0] = 22
[DEBUG]   R_T[1] = 22
[DEBUG]   R_T[2] = 103
[DEBUG]   W_T[0] = 5
[DEBUG]   W_T[1] = 33
[DEBUG]  Scaled epsilon values based on +20 percent guardband:
[DEBUG]   R_T[0] = 27
[DEBUG]   R_T[1] = 27
[DEBUG]   R_T[2] = 124
[DEBUG]   W_T[0] = 6
[DEBUG]   W_T[1] = 40
[INFO ]  starting istep 8.10
[INFO ]  starting istep 8.11
[INFO ]  starting istep 9.2
[INFO ]  starting istep 9.4
[INFO ]  starting istep 9.6
[INFO ]  starting istep 9.7
[INFO ]  starting istep 10.1
[INFO ]  starting istep 10.6
[INFO ]  starting istep 10.10
[INFO ]  starting istep 10.12
[INFO ]  starting istep 10.13
[DEBUG]  FFS header at 0x80060300ffff7000
[DEBUG]  PNOR base at 0x80060300fc000000
[DEBUG]  MEMD partition has ECC
[INFO ]  I2C transfer failed to complete (0x04011f0104000000)
[INFO ]  No memory DIMM at address 51
[INFO ]  I2C transfer failed to complete (0x04011f0104000000)
[INFO ]  No memory DIMM at address 52
[INFO ]  I2C transfer failed to complete (0x04011f0104000000)
[INFO ]  No memory DIMM at address 53
[INFO ]  I2C transfer failed to complete (0x04011f0104000000)
[INFO ]  No memory DIMM at address D4
[INFO ]  I2C transfer failed to complete (0x04011f0104000000)
[INFO ]  No memory DIMM at address D5
[INFO ]  I2C transfer failed to complete (0x04011f0104000000)
[INFO ]  No memory DIMM at address D6
[INFO ]  I2C transfer failed to complete (0x04011f0104000000)
[INFO ]  No memory DIMM at address D7
[DEBUG]  SPD @ 0x50
[INFO ]  SPD: module type is DDR4
[INFO ]  SPD: module part number is M393A1K43BB0-CRC    
[INFO ]  SPD: banks 16, ranks 1, rows 16, columns 10, density 8192 Mb
[INFO ]  SPD: device width 8 bits, bus width 64 bits
[INFO ]  SPD: module size is 8192 MB (per channel)
[INFO ]  starting istep 13.1
[INFO ]  starting istep 13.2
[INFO ]  starting istep 13.3
[INFO ]  starting istep 13.4
[INFO ]  starting istep 13.5
[INFO ]  starting istep 13.6
[INFO ]  starting istep 13.7
[INFO ]  starting istep 13.8
[INFO ]  starting istep 13.9
[INFO ]  starting istep 13.10
[DEBUG]  CCS took 2 us (3 us timeout), 1 instruction(s)
[DEBUG]  CCS took 2 us (2 us timeout), 14 instruction(s)
[DEBUG]  RCD dump for I2C address 0x58:
[DEBUG]  0xf820fa40: 80 b3 40 42 30 00 00 00 02 01 00 03 cb e3 c0 0d  ..@B0...........
[DEBUG]  0xf820fa50: 00 00 39 00 00 00 00 00 00 00 07 00 00 00 00 00  ..9.............
[INFO ]  starting istep 13.11
[DEBUG]  CCS took 2 us (7 us timeout), 2 instruction(s)
[DEBUG]  Write Leveling starting
[DEBUG]  CCS took 12 us (92 us timeout), 5 instruction(s)
[DEBUG]  Write Leveling done
[DEBUG]  Initial Pattern Write starting
[DEBUG]  CCS took 5 us (38 us timeout), 5 instruction(s)
[DEBUG]  Initial Pattern Write done
[DEBUG]  DQS alignment starting
[DEBUG]  CCS took 10 us (44 us timeout), 1 instruction(s)
[DEBUG]  DQS alignment done
[DEBUG]  Read Clock Alignment starting
[DEBUG]  CCS took 8 us (82 us timeout), 1 instruction(s)
[DEBUG]  Read Clock Alignment done
[DEBUG]  Read Centering starting
[DEBUG]  CCS took 36 us (120 us timeout), 1 instruction(s)
[DEBUG]  Read Centering done
[DEBUG]  Write Centering starting
[DEBUG]  CCS took 8236 us (11314 us timeout), 7 instruction(s)
[DEBUG]  Write Centering done
[DEBUG]  Coarse write/read starting
[DEBUG]  CCS took 5 us (24 us timeout), 1 instruction(s)
[DEBUG]  Coarse write/read done
[INFO ]  starting istep 13.12
[INFO ]  starting istep 13.13
[INFO ]  starting istep 14.1
[INFO ]  starting istep 14.2
[INFO ]  starting istep 14.3
[INFO ]  Initializing PEC0...
[INFO ]  Initializing PEC1...
[INFO ]  Initializing PEC2...
[INFO ]  Initializing PHB0...
[INFO ]  Initializing PHB1...
[INFO ]  Initializing PHB2...
[INFO ]  Initializing PHB3...
[INFO ]  Initializing PHB4...
[INFO ]  Initializing PHB5...
[INFO ]  starting istep 14.4
[INFO ]  starting istep 14.5
[WARN ]  0xF000F = 221d104900008040
[DEBUG]  CBMEM:
[DEBUG]  IMD: root @ 0xffeff000 254 entries.
[DEBUG]  IMD: root @ 0xffefec00 62 entries.
[DEBUG]  FMAP: area COREBOOT found @ 20200 (916992 bytes)
[DEBUG]  FFS header at 0x80060300ffff7000
[DEBUG]  PNOR base at 0x80060300fc000000
[DEBUG]  HBI partition has ECC
[INFO ]  CBFS: Found 'fallback/ramstage' @0x13ec0 size 0xeeeb in mcache @0xf8231080
[DEBUG]  TPM: Digest of `CBFS: fallback/ramstage` to PCR 2 logged
[DEBUG]  BS: romstage times (exec / console): total (unknown) / 24 ms


[NOTE ]  coreboot--TIMELESS--LESSTIME--Heads-v0.2.0-1501-g1a69b1d Thu Jan  1 00:00:00 UTC 1970 ramstage starting (log level: 7)...
[INFO ]  Enumerating buses...
[DEBUG]  Root Device scanning...
[DEBUG]  DD21, boot core: 18
[DEBUG]  FFS header at 0x80060300ffff7000
[DEBUG]  PNOR base at 0x80060300fc000000
[DEBUG]  HCODE partition has ECC
[DEBUG]  FFS header at 0x80060300ffff7000
[DEBUG]  PNOR base at 0x80060300fc000000
[DEBUG]  OCC partition has ECC
[DEBUG]  Base epsilon values read from table:
[DEBUG]   R_T[0] = 22
[DEBUG]   R_T[1] = 22
[DEBUG]   R_T[2] = 103
[DEBUG]   W_T[0] = 5
[DEBUG]   W_T[1] = 33
[DEBUG]  Scaled epsilon values based on +20 percent guardband:
[DEBUG]   R_T[0] = 27
[DEBUG]   R_T[1] = 27
[DEBUG]   R_T[2] = 124
[DEBUG]   W_T[0] = 6
[DEBUG]   W_T[1] = 40
[DEBUG]  FFS header at 0x80060300ffff7000
[DEBUG]  PNOR base at 0x80060300fc000000
[DEBUG]  WOFDATA partition has ECC
[NOTE ]  Matching WOF tables section not found, disabling WOF
[DEBUG]  Safe mode freq = 1833412 kHZ, voltage = 711 mv
[INFO ]  starting istep 15.2
[INFO ]  starting istep 15.3
[INFO ]  starting istep 15.4
[DEBUG]  Starting PM complex...
[DEBUG]  Attempting PGPE activation...
[DEBUG]  PGPE was activated successfully
[DEBUG]  Done starting PM complex
[INFO ]  starting istep 16.1
[DEBUG]  XIVE configured, entering dead man loop
[EMERG]  ASSERTION ERROR: file '(filenames not available on timeless builds)', line 404
[INFO ]  starting istep 18.11
[INFO ]  starting istep 18.12
[DEBUG]  Activating OCC...
[DEBUG]  Done activating OCC
[DEBUG]  CPU_CLUSTER: 0 enabled
[DEBUG]  PNP: 00e4.0 enabled
[DEBUG]  scan_bus: bus Root Device finished in 2507 msecs
[INFO ]  done
[DEBUG]  BS: BS_DEV_ENUMERATE run times (exec / console): 2499 / 9 ms
[INFO ]  Allocating resources...
[INFO ]  Reading resources...
[ERROR]  CPU_CLUSTER: 0 missing read_resources
[INFO ]  Done reading resources.
[ERROR]  CPU_CLUSTER: 0 missing set_resources
[DEBUG]  PNP: 00e4.0 00 <- [0x00000000000000e4 - 0x00000000000000e6] size 0x00000003 gran 0x00 io
[INFO ]  Done setting resources.
[INFO ]  Done allocating resources.
[DEBUG]  BS: BS_DEV_RESOURCES run times (exec / console): 0 / 2 ms
[INFO ]  Enabling resources...
[INFO ]  done.
[INFO ]  tpm_vendor_probe: ValidSts bit set(1) in TPM_ACCESS register after 0 ms
[DEBUG]  I2C TPM 2:20 (chip type slb9645tt device-id 0xD115)
[DEBUG]  TPM: Startup
[DEBUG]  TPM: command 0x99 returned 0x0
[DEBUG]  TPM: Asserting physical presence
[DEBUG]  TPM: command 0x4000000a returned 0x0
[DEBUG]  TPM: command 0x65 returned 0x0
[DEBUG]  TPM: flags disable=0, deactivated=0, nvlocked=0
[DEBUG]  TPM: Write digests cached in TPM log to PCR
[DEBUG]  TPM: Write digest for FMAP: FMAP into PCR 2
[DEBUG]  TPM: command 0x14 returned 0x0
[DEBUG]  TPM: Write digest for FMAP: BOOTBLOCK into PCR 2
[DEBUG]  TPM: command 0x14 returned 0x0
[DEBUG]  TPM: Write digest for CBFS: fallback/romstage into PCR 2
[DEBUG]  TPM: command 0x14 returned 0x0
[DEBUG]  TPM: Write digest for CBFS: fallback/ramstage into PCR 2
[DEBUG]  TPM: command 0x14 returned 0x0
[INFO ]  TPM: setup succeeded
[DEBUG]  BS: BS_DEV_INIT entry times (exec / console): 82 / 7 ms
[INFO ]  Initializing devices...
[DEBUG]  PNP: 00e4.0 init
[DEBUG]  IPMI: PNP BT 0xe4
[INFO ]  Get BMC self test result...Function Not Implemented
[INFO ]  IPMI: Found man_id 0x6cb0000, prod_id 0x1000000
[INFO ]  IPMI: Version 2.0
[DEBUG]  PNP: 00e4.0 init finished in 22 msecs
[INFO ]  Devices initialized
[DEBUG]  BS: BS_DEV_INIT run times (exec / console): 21 / 2 ms
[INFO ]  Finalize devices...
[INFO ]  Devices finalized
[DEBUG]  Writing coreboot table at 0xffed7000
[DEBUG]   0. 0000000000000000-00000000f8207fff: RAM
[DEBUG]   1. 00000000f8208000-00000000f820ffff: RAMSTAGE
[DEBUG]   2. 00000000f8210000-00000000f8ffffff: RAM
[DEBUG]   3. 00000000f9000000-00000000f92a1fff: RAMSTAGE
[DEBUG]   4. 00000000f92a2000-00000000ffed6fff: RAM
[DEBUG]   5. 00000000ffed7000-00000000ffefffff: CONFIGURATION TABLES
[DEBUG]   6. 00000000fff00000-00000001ff3fffff: RAM
[DEBUG]   7. 00000001ff400000-00000001ffffffff: RESERVED
[DEBUG]  FMAP: area COREBOOT found @ 20200 (916992 bytes)
[DEBUG]  FFS header at 0x80060300ffff7000
[DEBUG]  PNOR base at 0x80060300fc000000
[DEBUG]  HBI partition has ECC
[DEBUG]  Wrote coreboot table at: 0xffed7000, 0x240 bytes, checksum 98250000
[DEBUG]  coreboot table: 600 bytes.
[DEBUG]  IMD ROOT    0. 0xffeff000 0x00001000
[DEBUG]  IMD SMALL   1. 0xffefe000 0x00001000
[DEBUG]  CONSOLE     2. 0xffede000 0x00020000
[DEBUG]  TPM2 TCGLOG 3. 0xffedc000 0x00001180
[DEBUG]  MEM INFO    4. 0xffed9000 0x000022b0
[DEBUG]  COREBOOT    5. 0xffed7000 0x00002000
[DEBUG]  IMD small region:
[DEBUG]    IMD ROOT    0. 0xffefec00 0x00000400
[DEBUG]    RO MCACHE   1. 0xffefe960 0x00000298
[DEBUG]    FMAP        2. 0xffefe880 0x000000e0
[DEBUG]  BS: BS_WRITE_TABLES run times (exec / console): 1 / 8 ms
[INFO ]  CBFS: Found 'fallback/payload' @0x29440 size 0x63392 in mcache @0xffefeae4
[DEBUG]  TPM: Extending digest for `CBFS: fallback/payload` into PCR 2
[DEBUG]  TPM: command 0x14 returned 0x0
[DEBUG]  TPM: Digest of `CBFS: fallback/payload` to PCR 2 measured
[DEBUG]  Checking segment from ROM address 0xf8380000
[DEBUG]  Checking segment from ROM address 0xf838001c
[DEBUG]  Checking segment from ROM address 0xf8380038
[DEBUG]  Loading segment from ROM address 0xf8380000
[DEBUG]    code (compression=1)
[DEBUG]    New segment dstaddr 0x00000000 memsize 0x173c00 srcaddr 0xf8380054 filesize 0x6333e
[DEBUG]  Loading Segment: addr: 0x00000000 memsz: 0x0000000000173c00 filesz: 0x000000000006333e
[DEBUG]  using LZMA
[DEBUG]  Loading segment from ROM address 0xf838001c
[DEBUG]    BSS 0x00300000 (113776 byte)
[DEBUG]  Loading Segment: addr: 0x00300000 memsz: 0x000000000001bc70 filesz: 0x0000000000000000
[DEBUG]  it's not compressed!
[DEBUG]  Clearing Segment: addr: 0x0000000000300000 memsz: 0x000000000001bc70
[DEBUG]  Loading segment from ROM address 0xf8380038
[DEBUG]    Entry Point 0x00002570
[DEBUG]  BS: BS_PAYLOAD_LOAD run times (exec / console): 437 / 8 ms
[INFO ]  coreboot TPM 2.0 measurements:

[INFO ]   PCR-2 27c4f1fa214480c8626397a15981ef3a9323717f SHA1 [FMAP: FMAP]
[INFO ]   PCR-2 f4554638995ee526daf5925fad9cbdac4d51499d SHA1 [FMAP: BOOTBLOCK]
[INFO ]   PCR-2 c942f9f83e4bab89f048722dbfd05a6495ec231c SHA1 [CBFS: fallback/romstage]
[INFO ]   PCR-2 0b7a50ed49c6f0bee48b5f1f41558e8b22abd579 SHA1 [CBFS: fallback/ramstage]
[INFO ]   PCR-2 a0db7074b182bd4697e29599dbc3f6c3a807c8e4 SHA1 [CBFS: fallback/payload]

[DEBUG]  BS: BS_PAYLOAD_BOOT entry times (exec / console): 0 / 3 ms
[DEBUG]  Jumping to boot code at 0x00002570(0xffed7000)
[INFO ]  CBFS: Found '1-cpu.dtb' @0x23380 size 0x24e7 in mcache @0xffefea9c
[DEBUG]  TPM: Extending digest for `CBFS: 1-cpu.dtb` into PCR 2
[DEBUG]  TPM: command 0x14 returned 0x0
[DEBUG]  TPM: Digest of `CBFS: 1-cpu.dtb` to PCR 2 mea[    2.164832338,5] OPAL v6.3-rc2-32-gfa060c2c starting...
[    2.164835759,7] initial console log level: memory 7, driver 5
[    2.164837701,6] CPU: P9 generation processor (max 4 threads/core)
[    2.164839420,7] CPU: Boot CPU PIR is 0x004c PVR is 0x004e1201
[    2.164841927,7] OPAL table: 0x30108230 .. 0x30108810, branch table: 0x30002000
[    2.164844925,7] Assigning physical memory map table for nimbus
[    2.164847250,7] FDT: Parsing fdt @0xf90ab138
[    2.165553256,6] CHIP: Initialised chip 0 from xscom@603fc00000000
[    2.165577121,6] P9 DD2.10 detected
[    2.165578571,5] CHIP: Chip ID 0000 type: P9N DD2.10
[    2.165580618,7] XSCOM: Base address: 0x603fc00000000
[    2.165589265,7] XSTOP: XSCOM addr = 0x5012000, FIR bit = 31
[    2.165591372,6] MFSI 0:0: Initialized
[    2.165592714,6] MFSI 0:2: Initialized
[    2.165594093,6] MFSI 0:1: Initialized
[    2.165648741,6] LPC: LPC[000]: Initialized
[    2.165650135,7] LPC: access via MMIO @0x6030000000000
[    2.165663006,7] LPC: Default bus on chip 0x0
[    2.165669898,7] CPU: New max PIR set to 0x57
[    2.165700393,6] MEM: parsing reserved memory from node /reserved-memory
[    2.165704606,7] HOMER: Init chip 0
[    2.165706683,7]   PBA BAR0 : 0x00000001ff400000
[    2.165708348,7]   PBA MASK0: 0x0000000000300000
[    2.165710015,7]   HOMER Image at 0x1ff400000 size 4MB
[    2.165712632,7]   PBA BAR2 : 0x00000001ff800000
[    2.165714318,7]   PBA MASK2: 0x0000000000700000
[    2.165715944,7]   OCC Common Area at 0x1ff800000 size 8MB
[    2.165718240,7] CPU: decrementer bits 56
[    2.165722780,6] CPU: CPU from DT PIR=0x0048 Server#=0x48 State=3
[    2.165728423,6] CPU:  4 secondary threads
[    2.165731542,6] CPU: CPU from DT PIR=0x004c Server#=0x4c State=3
[    2.165736723,6] CPU:  4 secondary threads
[    2.165739766,6] CPU: CPU from DT PIR=0x0050 Server#=0x50 State=3
[    2.165745260,6] CPU:  4 secondary threads
[    2.165748235,6] CPU: CPU from DT PIR=0x0054 Server#=0x54 State=3
[    2.165753824,6] CPU:  4 secondary threads
[    2.165801758,6] PLAT: AST SIO unavailable!
[    2.165814408,7] UART: Using LPC IRQ 4
[    2.167888778,5] PLAT: Detected Talos platform
[    2.167930403,5] PLAT: Detected BMC platform ast2500:openbmc
[    2.182900296,5] CPU: All 16 processors called in...
[   11.288007582,7] LPC: Routing irq 10, policy: 0 (r=1)
[   11.288008691,7] LPC: SerIRQ 10 using route 0 targetted at OPAL
[   12.395741021,5] HIOMAP: Negotiated hiomap protocol v2
[   12.395817655,5] HIOMAP: Block size is 4KiB
[   12.395845286,5] HIOMAP: BMC suggested flash timeout of 8s
[   12.395888104,5] HIOMAP: Flash size is 64MiB
[   12.395931256,5] HIOMAP: Erase granule size is 4KiB
[   14.508165443,5] FLASH: Found system flash: (unnamed) id:0
[   15.298998889,3] STB: hw-key-hash not found
[   15.299053564,3] STB: hw_key-hash wrong size 0 (expected=64)
[   15.299118823,5] STB: Found tpm0,i2c_tpm_infineon evLogLen=608 evLogSize=4480
[   15.299202419,7] LPC: Routing irq 4, policy: 0 (r=1)
[   15.299203398,7] LPC: SerIRQ 4 using route 1 targetted at OPAL
[   15.299323523,5] OCC: All Chip Rdy after 0 ms
[   16.096568970,3] STB: VERSION NOT VERIFIED, invalid param. buf=0x30602188, len=4326 key-hash=0x0 hash-size=64
[   16.096673698,5] STB: VERSION hash calculated
[   16.181821090,5] STB: VERSION measured on pcr3 (tpm0, evType 0x5, evLogLen 687)
[   17.217692479,3] STB: IMA_CATALOG NOT VERIFIED, invalid param. buf=0x30604218, len=73728 key-hash=0x0 hash-size=64
[   17.218021408,5] STB: IMA_CATALOG hash calculated
[   17.303170696,5] STB: IMA_CATALOG measured on pcr2 (tpm0, evType 0x5, evLogLen 770)
[   18.004062541,3] CAPP: Error loading ucode lid. index=201d1

But then, no TPM:

┌────────────────────────┤ Talos 2 | Heads Boot Menu ├─────────────────────────┐
│ 2023-03-31 17:39:08 UTC                                                      │
│ TOTP: NO TPM | HOTP: N/A                                                     │
│                                                                              │
│                             d  Default boot                                  │
│                             r  Refresh TOTP/HOTP                             │
│                             o  Options -->                                   │
│                             s  System Info                                   │
│                             p  Power Off                                     │
│                                                                              │
│                                                                              │
│                     <Ok>                         <Cancel>                    │
│                                                                              │
└──────────────────────────────────────────────────────────────────────────────┘


@tlaurion
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cat /tmp/config:

export CONFIG_BOARD_NAME="Talos 2"
export CONFIG_BOOTSCRIPT="/bin/talos-init"
export CONFIG_BOOT_DEV="/dev/sda1"
export CONFIG_BOOT_EXTRA_TTYS="tty0"
export CONFIG_BOOT_KERNEL_ADD="console=tty0 console=hvc0 rootdelay=3 rootwait panic=10"
export CONFIG_BOOT_KERNEL_REMOVE="quiet"
export CONFIG_BOOT_REQ_HASH="n"
export CONFIG_BOOT_REQ_ROLLBACK="n"
export CONFIG_COREBOOT="y"
export CONFIG_COREBOOT_VERSION="talos_2"
export CONFIG_FLASHROM_OPTIONS="--noverify-all -p linux_mtd"
export CONFIG_LINUX_VERSION="5.5-openpower"
export CONFIG_TPM="y"
export CONFIG_USB_KEYBOARD="y"
export CONFIG_USE_AGETTY="y"
export GIT_HASH='1a69b1dd079933f093140ef0e952dfd55d11fe90'
export GIT_STATUS=clean
export CONFIG_BOARD=talos-2
export CONFIG_BOOT_DEV="/dev/nvme0n1p2"
export CONFIG_TPM2_TOOLS=""
export CONFIG_TPM="y"
export CONFIG_TPM="n"
export CONFIG_TPM2_TOOLS="n"

Meaning that dynamic code detection for TPM was triggered because no tpm was found.

~ # grep -Rn tpm init 
59:if [ ! -e /dev/tpm0 ]; then
75:	# Initialize tpm2 encrypted sessions here
76:	tpmr startsession
118:		tpmr extend -ix 4 -ic recovery
177:	tpmr extend -ix 4 -ic recovery
~ # ls /dev/tpm0
ls: /dev/tpm0: No such file or directory

@krystian-hebel And this is because linux didn't find the tpm nor created /dev/tpm0

@tlaurion
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ls: /dev/tpm0: No such file or directory
~ # dmesg | grep -i tpm
[    4.742973] ima: No TPM chip found, activating TPM-bypass!

@tlaurion
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tlaurion commented Apr 3, 2023

@krystian-hebel
[INFO ] coreboot TPM 2.0 measurements:

Hmmm.
Edit: all logs above prints from coreboot tpm2 codepaths.

@tlaurion
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tlaurion commented Apr 3, 2023

@krystian-hebel #1362 is merged, fixing usb keyboard which were tested with https://app.circleci.com/pipelines/github/tlaurion/heads/1580/workflows/16321a18-0fb8-4cbf-ad49-c5d0ec6c5288/jobs/20158/artifacts

This PR should be rebased on top of master when some more troubleshooting done on my platform from your side.

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tlaurion commented Apr 3, 2023

@krystian-hebel since thi PR fixes successfully the issue it was targeting, would you want me to open new issues upstream for TPM being unreliable and we merge+close this, or is it easier for you to add more commits here for me to test?


As of now, which might need a seperate issue:

  • TPM is detected reliably by coreboot on Heads reboot
  • skiboot seems consistent on TPM being accessible
  • Heads doesn't seem to be able to talk reliably to TPM

@krystian-hebel
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@tlaurion since I don't have ideas what can be wrong with that TPM and what can be checked right now I think we can merge it as it is and get back to debugging later, if that's OK with you.

[INFO ] coreboot TPM 2.0 measurements:

Yes, this is because Skiboot doesn't understand TPM1.2 log format. Its whole approach to extending PCRs is specific, to say the least, but as I understand it, specifications don't forbid it. What Skiboot does is it hashes blocks of memory using SHA512, but extends PCR banks for SHA1 and SHA256 (only SHA1 in TPM1.2, added by us) with appropriate number of first bytes of SHA512. It has the advantage of not having to hash the data twice.

@tlaurion tlaurion merged commit a447674 into linuxboot:master Apr 3, 2023
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tlaurion commented Apr 3, 2023

@krystian-hebel issues should be opened linking to previous comments on Dasharo side for TPM issues.

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