Verilog IPs Core for Vivado

GitHub repository: https://github.com/lgili/xilinx-ip-repo

Introduction

This is a basic AXIs IP core, written in Verilog with cocotb testbenches.

Documentation

To build a IP

First you need to export the vivado sources

$ source /tools/Xilinx/Vivado/2021.1/settings64.sh

After you can enter in the IP folder and do Make

$ make

Then you need to add this folter to yours IP repository on Vivado.

To run simulation with cocotb

$ make
$ gtkwave sim.fst