- 🌱 I’m currently focusing on ASIC design.
- 🔭 I obtained my bachelor's degree from Shenzhen University, and I am currently pursuing a master's degree at Zhengzhou University.
- 🏢 I interned at the Beijing Institute of Open Source Chip from 2023 to 2024 as a Digital IC Design and Verification Engineer, focusing on DDR Subsystem.
- 📫 How to reach me: lauchinyuan@yeah.net or 2018133098@email.szu.edu.cn
🤯
(⌐⚪_⚪) working!
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Zhengzhou University
- Zhengzhou, China
- https://lauchinyuan.github.io/
- channel/UCgZzwGbKnsISU2mJxxyopVw
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FPGA_QPSK-modem
FPGA_QPSK-modem PublicA QPSK modem written in the Verilog hardware description language, that can be implemented on FPGA
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Booth4_wallace_MULT16_16
Booth4_wallace_MULT16_16 PublicA 16-bit by 16-bit signed binary multiplier based on the Radix-4 Booth algorithm and Wallace Tree reduction
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Asymmetric_async_FIFO
Asymmetric_async_FIFO Publicasynchronous FIFO that support Non-symmetric aspect ratios(different read and write data widths), First-Word Fall-Through and data counter.
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Pytorch_NN_Quant_to_FPGA
Pytorch_NN_Quant_to_FPGA PublicUsing pytorch to realize neural network quantization, parameter export and FPGA/ASIC fixed-point arithemetic simulation
198 contributions in the last year
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Contributed to
lauchinyuan/lauchinyuan,
lauchinyuan/Pytorch_NN_Quant_to_FPGA,
lauchinyuan/Booth4_wallace_MULT16_16
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March 2025
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