riscv: Reposition .rodata to after .bss

Previously having .rodata before .data was causing the 32-bit spike simulation on QEMU to freeze up before entering the elfloader. Positioning .rodata just after .bss as was the case before 6531c8e fixes the issue. Signed-off-by: Damon Lee <[email protected]>
kent-mcleod · May 24, 2021 · 8de8c9f · 8de8c9f
1 parent 95b3766
commit 8de8c9f
Showing 1 changed file with 26 additions and 0 deletions.
diff --git a/elfloader-tool/src/arch-riscv/linker.lds b/elfloader-tool/src/arch-riscv/linker.lds
@@ -4,6 +4,13 @@
  * SPDX-License-Identifier: GPL-2.0-only
  */
 
+/*
+ * NOTE: For RISC-V 32-bit, having the .rodata section before the .data section causes the elfloader to
+ *       freeze up. Thus, for 32-bit we move the .rodata section to after the .bss section as previously
+ *       before some refactoring. The 64-bit version does not seem to be affect by this issue and uses thus
+ *       uses the new layout.
+ */
+
 #include <autoconf.h>
 #include <elfloader/gen_config.h>
 #include "image_start_addr.h"
@@ -22,6 +29,7 @@ SECTIONS
     {
         *(.text)
     }
+#ifdef CONFIG_ARCH_RISCV64
     . = ALIGN(16);
     .rodata :
     {
@@ -37,6 +45,7 @@ SECTIONS
         *(._archive_cpio)
         _archive_end = .;
     }
+#endif
     . = ALIGN(16);
     .data :
     {
@@ -54,5 +63,22 @@ SECTIONS
         *(.bss.*)
         _bss_end = .;
     }
+#ifdef CONFIG_ARCH_RISCV32
+    . = ALIGN(16);
+    .rodata :
+    {
+        *(.srodata*)
+        . = ALIGN(16);
+        *(.rodata)
+        *(.rodata.*)
+        /*
+         * ld crashes when we add this here: *(_driver_list)
+         */
+        . = ALIGN(16);
+        _archive_start = .;
+        *(._archive_cpio)
+        _archive_end = .;
+    }
+#endif
      _end = .;
 }