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feat(cuda-ep): native PagedAttention LATENT kernel for GLM-5.2 dense MLA (slice 3A.2) - #1978
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…aints Gaff follow-up on #1955: make LatentCacheGeometry::validate mirror the op's LATENT-path checks completely. In addition to the existing rotary_dim % 16 (cos/sin cache derivation), enforce: - latent_dim % 8 == 0 (op treats latent_dim as head_size; check_q_k_latent), - rotary_offset % 8 == 0 (check_inputs rotary_offset contract). Adds tests for the two new rejections and the accepted rotary_offset==0 case. Refuses at the KV seam a geometry the op would reject downstream. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
… GLM-5.2 dense MLA (slice 3A.2) Add a native CUDA kernel for the ORT v1 `com.microsoft::PagedAttention` LATENT subset needed by GLM-5.2 dense MLA, gated behind a typed geometry validator. Default-off: the kernel claims an op only when the validator proves the exact supported subset (fp16/bf16 LATENT, single latent KV head, in-place key_cache alias); every unsupported optional mode returns a typed NotImplemented reason instead of silently miscomputing. - New `kernels/paged_attention.rs`: NVRTC f16/bf16 write+attention kernels implemented from the oracle equations (partial-RoPE suffix, online softmax over the paged latent cache, leading v_head_size V channels), `PagedAttentionFactory`, `PagedAttentionLatentKernel` (capture/replay safe: warmed signature, no host sync/alloc in capture), and `unsupported_reason()` typed rejections. - Five-place op registration in `kernels/mod.rs` (module, covered ops, dtype table, factory) and the `unsupported_reason` arm in `provider.rs::supports_op`. - `onnx-genai-kv` remains the sole page/cache authority; no op-side allocation or second manager. In-place `key_cache_out` alias contract enforced (rejects non-aliased cache output). - Typed rejections: non-LATENT layout, quantized cache, head_sink, q/k-norm, k/v scales, present value/value_cache, non-f16/bf16. Tests (native CUDA vs `onnx-genai-paged-attention` oracle on A100): tiny prefill/decode, GLM dims (qk=192/v=128/partial RoPE) first token/prefill/decode, block pow2>=16 boundary + multi-request, slot -1 skip, no-rotary, eager equivalence, capture + 3 replays bit-equal to eager, alias + missing-input rejections, and a tiny-shape CUDA-event measurement (prefill/decode, n=5, page/VRAM accounting, no full-size claim). Five pure unit tests cover typed rejections without a GPU. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
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Additional details and impacted files@@ Coverage Diff @@
## main #1978 +/- ##
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+ Coverage 80.21% 80.23% +0.02%
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Files 421 422 +1
Lines 203480 203638 +158
Branches 203480 203638 +158
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+ Hits 163231 163399 +168
+ Misses 34675 34670 -5
+ Partials 5574 5569 -5
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…w findings) Independent review (excluding Leon/Sapper) found no high-severity issues; these address the medium/low defensive findings so every geometry/dtype mismatch fails with a typed error instead of miscomputing or faulting. - execute(): cross-check the attribute-derived geometry (num_heads, head_size, batch) against the actual query/key/cumulative_sequence_length extents. Previously a schema-typed but geometry-inconsistent node (e.g. a num_heads attribute disagreeing with the query hidden dim) drove out-of-bounds device reads that tear down the CUDA context; now it returns a typed KernelFailed like the kernel's other geometry checks. - unsupported_reason(): reject kv_num_heads != 1 at the supports_op gate so a multi-head-KV node is routed elsewhere rather than claimed then hard failing at kernel creation. Keeps the claim/reject decision consistent with create()/execute(). - execute(): validate sin_cache dtype symmetrically with cos_cache. Tests: new unit test rejects_multi_head_kv; extend the GPU rejection test with a num_heads geometry-mismatch case. Full GPU suite (10) + unit tests (6) green on A100; parity/capture/measurement unchanged. Co-authored-by: Copilot <223556219+Copilot@users.noreply.github.com>
Independent review round (pre-request, reviewer excluding Leon/Sapper)An independent code-review pass (read + build, traced every math path against
Three defensive findings (1 Medium, 1 Low, 1 nit) were fixed in
New tests: unit Still a draft — final approval required from Gaff or Roy (not Leon/Sapper). Remaining gate: full-size GLM checkpoint runs (coordinated with the GLM GGUF/safetensors work); 3B Mobius opt-in export starts only after 3A approval. |
Independent review verdict — PR #1978 (native CUDA
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Slice 3A.2 — native onnx-genai CUDA support for
com.microsoft::PagedAttentionLATENT (GLM-5.2 dense MLA)Builds on the merged audit/validator/oracle (#1940) and the token-major/LATENT KV index emission (#1955). This slice adds the native CUDA kernel for the exact ORT v1
com.microsoft::PagedAttentionLATENT (absorbed-MLA) subset that GLM-5.2 dense MLA needs, withonnx-genai-kvremaining the sole page/cache authority.Depends on / stacks after #1955 (already merged into
main).What this adds
crates/onnx-runtime-ep-cuda/src/kernels/paged_attention.rs— NVRTC f16/bf16 write + attention kernels implemented from the oracle equations (not copied upstream source): partial-RoPE suffix write into the paged latent cache, online softmax over the latent cache honoringlocal_window_size/softcap, V taken from the leadingv_head_sizechannels of the same latent row. PlusPagedAttentionFactory,PagedAttentionLatentKernel, andunsupported_reason().kernels/mod.rs+ theunsupported_reasonarm inprovider.rs::supports_op.Invariants held
head_sink, q/k-norm, k/v scales, presentvalue/value_cache, non-f16/bf16.key_cache_outalias contract enforced (non-aliased cache output is rejected).Tests (native CUDA vs
onnx-genai-paged-attentionoracle, verified on an idle A100)-1skip; no-rotary; eager equivalence (fp16 err ~2e-4, bf16 ~2e-3 — well under tol).check_capture_error()==0).key_cache_outand missing required input (block_table).onnx-runtime-ep-cudalib suite green (559 passed) — no regressions; KV geometry validation (feat(kv): token-major/LATENT PagedAttention index emission (slice 3A.1) #1955 + Gaff's sibling constraints) unchanged.Reviewer / gates
--paged-attentionexport only starts after 3A approval.GPU tests are gated behind the
gpu-testscargo feature and the CUDA env; run on A100 with--features gpu-tests.