FPGA & Computer Architecture
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SpiceEngine CEO / TokyoTech
- Japan
- https://www.jinguji.me/
- https://orcid.org/0000-0001-5691-3472
- @jin0g
Pinned Loading
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ap_vector
ap_vector PublicA powerful integer vector computation library designed for Vitis HLS.
C++
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speedlogger
speedlogger PublicSpeedLogger: A Python tool to monitor and log internet speeds using WandB.
Python 1
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Optune example of Multi-node, Resume...
Optune example of Multi-node, Resume, Early-stopping with Chainer MNIST 1# here mnist.py
2from chainer import Function, report, training, utils, Variable
3from chainer import Link, Chain, ChainList, Sequential
4from chainer import datasets, iterators, optimizers, serializers
5from chainer.datasets import mnist
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PYNQ_EXAMPLE_DMA_MULADD.ipynb
PYNQ_EXAMPLE_DMA_MULADD.ipynb 1{
2"cells": [
3{
4"cell_type": "markdown",
5"metadata": {},
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April 2025
Created 7 commits in 1 repository
Opened 1 pull request in 1 repository
jin0g/actiontest
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Feature/hls python test
This contribution was made on Apr 17
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