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[water] Bump LLVM #403

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tgymnich wants to merge 5 commits into from
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[water] Bump LLVM #403

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7bfc663
update amdgpu.mfma op
tgymnich Oct 30, 2025
9887923
bump llvm
tgymnich Oct 30, 2025
b5dfa4f
Update ci-gpu.yaml
tgymnich Oct 30, 2025
be80d66
[water] Revamp RegionBranchOpInterface
tgymnich Oct 30, 2025
d5e6bfa
set MLIR_BINDINGS_PYTHON_INSTALL_PREFIX
tgymnich Nov 14, 2025
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2 changes: 1 addition & 1 deletion .github/workflows/ci-gpu.yaml
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Expand Up @@ -24,7 +24,7 @@ concurrency:

env:
LLVM_SHA_FILE: llvm-sha.txt
LLVM_CACHE_NUMBER: 1 # Increase to reset cache
LLVM_CACHE_NUMBER: 2 # Increase to reset cache

jobs:
# Water uses its own LLVM version independent of the one used by IREE and
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6 changes: 3 additions & 3 deletions water/lib/Dialect/Wave/IR/WaveOps.cpp
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Expand Up @@ -112,15 +112,15 @@ bool wave::IterateOp::areTypesCompatible(mlir::Type lhs, mlir::Type rhs) {
}

mlir::OperandRange
wave::IterateOp::getEntrySuccessorOperands(mlir::RegionBranchPoint point) {
wave::IterateOp::getEntrySuccessorOperands(mlir::RegionSuccessor successor) {
return getIterArgs();
}

void wave::IterateOp::getSuccessorRegions(
mlir::RegionBranchPoint point,
::llvm::SmallVectorImpl<::mlir::RegionSuccessor> &regions) {
// May branch into the region or bypass it regardless of the source.
regions.emplace_back(mlir::RegionSuccessor(getResults()));
regions.emplace_back(mlir::RegionSuccessor(getOperation(), getResults()));
regions.emplace_back(
mlir::RegionSuccessor(&getBody(), getBody().front().getArguments()));
}
Expand Down Expand Up @@ -544,6 +544,6 @@ LogicalResult WriteOp::verify() {
//-----------------------------------------------------------------------------

mlir::MutableOperandRange
wave::YieldOp::getMutableSuccessorOperands(mlir::RegionBranchPoint) {
wave::YieldOp::getMutableSuccessorOperands(mlir::RegionSuccessor) {
return getValuesMutable();
}
2 changes: 1 addition & 1 deletion water/llvm-sha.txt
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@@ -1 +1 @@
ec3cf67434ba361124cfbb548e93589acd0d3cf2
1e3a1ce911d1e5e3804b63e3ba3059c36eb697e5
1 change: 1 addition & 0 deletions water/python/CMakeLists.txt
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Expand Up @@ -9,6 +9,7 @@ if (WATER_ENABLE_PYTHON)

# Avoid clashing with IREE Python bindings
set(MLIR_BINDINGS_PYTHON_NB_DOMAIN "water_mlir")
set(MLIR_BINDINGS_PYTHON_INSTALL_PREFIX "python_packages/water/water_mlir" CACHE STRING "" FORCE)
add_compile_definitions("MLIR_PYTHON_PACKAGE_PREFIX=water_mlir.")

declare_mlir_python_sources(WaterPythonSources)
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4 changes: 2 additions & 2 deletions water/test/Transforms/lowered_gemm_pipelined.mlir
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Expand Up @@ -55,8 +55,8 @@ module attributes {transform.with_named_sequence} {
%58 = vector.load %view[%5, %7] : memref<64x36xbf16, #gpu.address_space<workgroup>>, vector<8xbf16>
%59 = vector.load %view_4[%8, %6] : memref<64x36xbf16, #gpu.address_space<workgroup>>, vector<8xbf16>
%60 = vector.load %view_4[%8, %7] : memref<64x36xbf16, #gpu.address_space<workgroup>>, vector<8xbf16>
%61 = amdgpu.mfma %59 * %57 + %arg4 {blocks = 1 : i32, k = 16 : i32, m = 32 : i32, n = 32 : i32} blgp = none : vector<8xbf16>, vector<8xbf16>, vector<16xf32>
%62 = amdgpu.mfma %60 * %58 + %61 {blocks = 1 : i32, k = 16 : i32, m = 32 : i32, n = 32 : i32} blgp = none : vector<8xbf16>, vector<8xbf16>, vector<16xf32>
%61 = amdgpu.mfma 32x32x16 %59 * %57 + %arg4 {blocks = 1 : i32} blgp = none : vector<8xbf16>, vector<8xbf16>, vector<16xf32>
%62 = amdgpu.mfma 32x32x16 %60 * %58 + %61 {blocks = 1 : i32} blgp = none : vector<8xbf16>, vector<8xbf16>, vector<16xf32>
scf.yield %62, %arg7, %arg8, %55, %56 : vector<16xf32>, vector<8xbf16>, vector<8xbf16>, vector<8xbf16>, vector<8xbf16>
}
%16 = vector.extract_strided_slice %15#0 {offsets = [0], sizes = [1], strides = [1]} : vector<16xf32> to vector<1xf32>
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