eBPF.md: Document atomic [fetch-and-]{and,or,xor} instructions

The instructions are selected when the immediate field of an atomic
instruction is set to BPF_OR (0x40), BPF_AND (0x50), or BPF_XOR (0xa0),
instead of BPF_ADD (0), and can possibly get the BPF_FETCH (1) flag as
well.

This is supported in the kernel since commit:
981f94c3e921 ("bpf: Add bitwise atomic instructions")

eBPF.md

@@ -233,7 +233,13 @@ Opcode | Mnemonic            | Pseudocode
 Opcode             | Mnemonic                   | Pseudocode
 -------------------|----------------------------|---------------------------------------------------------
 0xdb (imm == 0x00) | add [dst+off], src         | (dst + off) += src
+0xdb (imm == 0x40) | or [dst+off], src          | (dst + off) \|= src
+0xdb (imm == 0x50) | and [dst+off], src         | (dst + off) &= src
+0xdb (imm == 0xa0) | xor [dst+off], src         | (dst + off) ^= src
 0xdb (imm == 0x01) | fetch_add [dst+off], src   | src = dst, (dst + off) += src
+0xdb (imm == 0x41) | fetch_or [dst+off], src    | src = dst, (dst + off) \|= src
+0xdb (imm == 0x51) | fetch_and [dst+off], src   | src = dst, (dst + off) &= src
+0xdb (imm == 0xa1) | fetch_xor [dst+off], src   | src = dst, (dst + off) ^= src
 0xdb (imm == 0xe1) | xchg [dst+off], src        | src = (dst + off), (dst + off) = src
 0xdb (imm == 0xf1) | cmpxchg [dst+off], src     | r0 = (dst + off), (dst + off) = src if (dst + off) == r0
 
@@ -242,6 +248,12 @@ Opcode             | Mnemonic                   | Pseudocode
 Opcode             | Mnemonic                   | Pseudocode (uint32_t * casts omitted for readability)
 -------|----------------------------|---------------------------------------------------------------------
 0xc3 (imm == 0x00) | add32 [dst+off], src       | (dst + off) += src
+0xc3 (imm == 0x40) | or32 [dst+off], src        | (dst + off) \|= src
+0xc3 (imm == 0x50) | and32 [dst+off], src       | (dst + off) &= src
+0xc3 (imm == 0xa0) | xor32 [dst+off], src       | (dst + off) ^= src
 0xc3 (imm == 0x01) | fetch_add32 [dst+off], src | src = dst, (dst + off) += src
+0xc3 (imm == 0x41) | fetch_or32 [dst+off], src  | src = dst, (dst + off) \|= src
+0xc3 (imm == 0x51) | fetch_and32 [dst+off], src | src = dst, (dst + off) &= src
+0xc3 (imm == 0xa1) | fetch_xor32 [dst+off], src | src = dst, (dst + off) ^= src
 0xc3 (imm == 0xe1) | xchg32 [dst+off], src      | src = (dst + off), (dst + off) = src
 0xc3 (imm == 0xf1) | cmpxchg32 [dst+off], src   | r0 = (dst + off), (dst + off) = src if (dst + off) == r0