[SYCL][Doc] Update SYCL_INTEL_data_flow_pipes extension for FPGA host…#8789
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steffenlarsen merged 13 commits intointel:syclfrom Mar 30, 2023
Merged
[SYCL][Doc] Update SYCL_INTEL_data_flow_pipes extension for FPGA host…#8789steffenlarsen merged 13 commits intointel:syclfrom
steffenlarsen merged 13 commits intointel:syclfrom
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This was referenced Mar 27, 2023
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@rho180 , can you please take a look at this Spec? |
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rho180
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Co-authored-by: Steffen Larsen <steffen.larsen@intel.com>
gmlueck
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steffenlarsen
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Thanks @zibaiwan! LGTM!
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@steffenlarsen , thanks for your review. The test passed for the doc change. |
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A continuation of #5838. Accompanying runtime change is #7468.
Add a memory order parameter to device-side read/write members and
default to sycl::memory_order::seq_cst. This parameter is in place but not being used at this moment, it's intended for the future work.
Add host pipe read/write members with additional sycl::queue parameter.