[SYCL] Use new vec/swizzle in preview mode
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Before this PR it could only be enabled by explicitly defining a macro, now it's on by default in preview. We plan on keeping the macro to allow using old implementation until the first minor release after the next major one.
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| // CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr addrspace(4) [[INP]], align 2, !tbaa [[TBAA11]], !noalias [[META25]] | ||
| // CHECK-NEXT: [[CALL_I_I_I_I:%.*]] = tail call spir_func noundef i32 @__imf_bfloat162int_rn(i16 noundef zeroext [[TMP0]]) #[[ATTR4]], !noalias [[META25]] | ||
| // CHECK-NEXT: store i32 [[CALL_I_I_I_I]], ptr addrspace(4) [[AGG_RESULT]], align 4, !alias.scope [[META25]] | ||
| // CHECK-NEXT: [[RESULT_I:%.*]] = alloca %"class.sycl::_V1::vec.108", align 4 |
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Just wondering about why's the device code generated with the new implementation much bigger than the older one?
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Missed this one, will look.
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I have a fix, will upload it once this is merged (so that the change would be visible in the tests).
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uditagarwal97
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Before this PR it could only be enabled by explicitly defining a macro, now it's on by default in preview. We plan on keeping the macro to allow using old implementation until the first minor release after the next major one.