[SYCL][CUDA] Unoptimized stream regression test #362
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Previously the CUDA backend would fail due to invalid atomic memory orders not being optimized out. The use of these invalid memory orders have been removed in recent changes, so this commit adds a regression test to make sure they do not resurface. Signed-off-by: Steffen Larsen <[email protected]>
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Previously the CUDA backend would fail due to invalid atomic memory orders not being optimized out. The use of these invalid memory orders have been removed in intel/llvm#4106, so this commit adds a regression test to make sure they do not resurface.
The test look good to me.
I would add the motivation to have this regression test to code comments instead of (or in addition to) the commit message.
Good call! I'll add that once all the tests finish. Can you confirm that the only failing test in Jenkins/pre-ci-cuda is the new test? If so it should work when intel/llvm#4106 is merged. |
Yes. Only new test fails with fatal error: error in backend: Cannot select: t3: i32,ch = AtomicLoad<(volatile load seq_cst (s32) from %ir.0, addrspace 1)> t0, t2
t2: i64,ch = CopyFromReg t0, Register:i64 %0
t1: i64 = Register %0
In function: _ZNK2cl4sycl6atomicIjLNS0_6access13address_spaceE1EE4loadIjEENSt9enable_ifIXntsr3std7is_sameIfT_EE5valueEjE4typeENS0_12memory_orderE
Let's re-run the test after intel/llvm#4106 is merged to confirm that. |
Signed-off-by: Steffen Larsen <[email protected]>
Previously the CUDA backend would fail due to invalid atomic memory orders not being optimized out. The use of these invalid memory orders have been removed in recent changes, so this commit adds a regression test to make sure they do not resurface. Signed-off-by: Steffen Larsen <[email protected]>
…e#362) Previously the CUDA backend would fail due to invalid atomic memory orders not being optimized out. The use of these invalid memory orders have been removed in recent changes, so this commit adds a regression test to make sure they do not resurface. Signed-off-by: Steffen Larsen <[email protected]>
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Previously the CUDA backend would fail due to invalid atomic memory orders not being optimized out. The use of these invalid memory orders have been removed in intel/llvm#4106, so this commit adds a regression test to make sure they do not resurface.