Create DPAS Analysis infrastructure#1558
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Signed-off-by: Tiotto, Ettore <ettore.tiotto@intel.com>
etiotto
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Jul 3, 2024
Signed-off-by: Tiotto, Ettore <ettore.tiotto@intel.com>
etiotto
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Jul 3, 2024
etiotto
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Jul 3, 2024
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| namespace mlir::triton::gpu::intel { | ||
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| enum class DeviceArch { |
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Note: moved to Utility.h
Signed-off-by: Tiotto, Ettore <ettore.tiotto@intel.com>
Signed-off-by: Tiotto, Ettore <ettore.tiotto@intel.com>
Signed-off-by: Tiotto, Ettore <ettore.tiotto@intel.com>
Signed-off-by: Tiotto, Ettore <ettore.tiotto@intel.com>
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chengjunlu
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victor-eds
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Looks to me we don't need a map at all. We can just:
- Check precondition (attribute+threads per warp)
- Walk and check each dot operation supports dpas:
- If an operation does not support it, set a member to
False, exit - If an operation potentially does not support it, set some member to
MayBe
- If an operation does not support it, set a member to
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We do not necessarily need the map but I want to keep it to have the flexibility to identify which tt.dot operations can be lowered to DPAS instructions. We might want to use that flexibility later. |
Signed-off-by: Tiotto, Ettore <ettore.tiotto@intel.com>
Signed-off-by: Tiotto, Ettore <ettore.tiotto@intel.com>
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Create a
DPASAnalysisclass that analyzes a function (e.g. kernel) and determines whethertt.dotoperations can be lowered to DPAS instructions on ATS/PVC target. In this PR we replace uses ofsupportDPASwith a public member function provided by the new class. A future PR will use the same infrastructure to change the subgroup size in the module if the analysis detects that a kernel containstt.dotoperations that would be optimizable (could be lowered to DPAS instructions) if the subgroup size was the one supported by the DPAS instruction for the target architecture (e.g. 16 on PVC).