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[GEN] Allow tile width of 32 bits 2Dblockload to be 16#1280

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whitneywhtsang merged 1 commit intollvm-targetfrom
whitneywhtsang/2dblock_32bitverify
Jun 7, 2024
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[GEN] Allow tile width of 32 bits 2Dblockload to be 16#1280
whitneywhtsang merged 1 commit intollvm-targetfrom
whitneywhtsang/2dblock_32bitverify

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Signed-off-by: Whitney Tsang <whitney.tsang@intel.com>
@whitneywhtsang whitneywhtsang self-assigned this Jun 7, 2024
@whitneywhtsang whitneywhtsang changed the title [GEN] Allow tile width of 32 bits 2DBlockRead to be 16 [GEN] Allow tile width of 32 bits 2DBlockLoad to be 16 Jun 7, 2024
@whitneywhtsang whitneywhtsang changed the title [GEN] Allow tile width of 32 bits 2DBlockLoad to be 16 [GEN] Allow tile width of 32 bits 2Dblockload to be 16 Jun 7, 2024
@whitneywhtsang whitneywhtsang merged commit a839380 into llvm-target Jun 7, 2024
@whitneywhtsang whitneywhtsang deleted the whitneywhtsang/2dblock_32bitverify branch June 7, 2024 04:36
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Please revert.

Comment thread test/TritonGEN/tritongen-invalid.mlir
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etiotto commented Jun 7, 2024

btw what is the issue attached to the PR?

wdziurdz pushed a commit that referenced this pull request Apr 7, 2026
Automated merge of main-interim into main-cri. Do not squash!
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[TritonGEN]: Improve diagnostic for 2D block load/store operations.

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