Add 64-bit RISC-V support

Signed-off-by: Martin Kröning <[email protected]>

Cargo.toml

@@ -21,5 +21,8 @@ x86_64 = { version = "0.14", default-features = false, features = [ "instruction
 aarch64-cpu = "9.0"
 tock-registers = { version = "0.8", default-features = false }
 
+[target.'cfg(target_arch = "riscv64")'.dependencies]
+riscv = "0.10"
+
 [dev-dependencies]
 rand = "0.8"

src/interrupts.rs

@@ -102,3 +102,29 @@ mod imp {
         DAIF.set(value);
     }
 }
+
+#[cfg(target_arch = "riscv64")]
+mod imp {
+    use riscv::register::sstatus;
+
+    pub type Flags = bool;
+    pub type AtomicFlags = core::sync::atomic::AtomicBool;
+
+    pub const DISABLE: bool = false;
+
+    #[inline]
+    pub fn get() -> bool {
+        sstatus::read().sie()
+    }
+
+    #[inline]
+    pub fn set(value: bool) {
+        unsafe {
+            if value {
+                sstatus::set_sie();
+            } else {
+                sstatus::clear_sie();
+            }
+        }
+    }
+}