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ARM: dts: uniphier: add outer cache controller nodes
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Add L2 cache controller nodes for all the UniPhier SoC DTSI.
Also, add an L3 cache controller node for PH1-Pro5 DTSI.

Signed-off-by: Masahiro Yamada <[email protected]>
Signed-off-by: Olof Johansson <[email protected]>
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@masahir0y @olofj
masahir0y authored and olofj committed Oct 27, 2015
1 parent 3d2ef3b commit 7c62f29
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Showing 6 changed files with 97 additions and 0 deletions.
13 changes: 13 additions & 0 deletions arch/arm/boot/dts/uniphier-ph1-ld4.dtsi
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Expand Up @@ -55,6 +55,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
next-level-cache = <&l2>;
};
};

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#size-cells = <1>;
};

l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
interrupts = <0 174 4>, <0 175 4>;
cache-unified;
cache-size = <(512 * 1024)>;
cache-sets = <256>;
cache-line-size = <128>;
cache-level = <2>;
};

serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
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14 changes: 14 additions & 0 deletions arch/arm/boot/dts/uniphier-ph1-pro4.dtsi
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Expand Up @@ -56,12 +56,14 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
next-level-cache = <&l2>;
};

cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
next-level-cache = <&l2>;
};
};

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#size-cells = <1>;
};

l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
interrupts = <0 174 4>, <0 175 4>;
cache-unified;
cache-size = <(768 * 1024)>;
cache-sets = <256>;
cache-line-size = <128>;
cache-level = <2>;
};

serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
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27 changes: 27 additions & 0 deletions arch/arm/boot/dts/uniphier-ph1-pro5.dtsi
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Expand Up @@ -56,12 +56,14 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
next-level-cache = <&l2>;
};

cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
next-level-cache = <&l2>;
};
};

Expand Down Expand Up @@ -98,6 +100,31 @@
#size-cells = <1>;
};

l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x8>,
<0x506c0000 0x400>;
interrupts = <0 190 4>, <0 191 4>;
cache-unified;
cache-size = <(2 * 1024 * 1024)>;
cache-sets = <512>;
cache-line-size = <128>;
cache-level = <2>;
next-level-cache = <&l3>;
};

l3: l3-cache@500c8000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c8000 0x2000>, <0x503c8100 0x8>,
<0x506c8000 0x400>;
interrupts = <0 174 4>, <0 175 4>;
cache-unified;
cache-size = <(2 * 1024 * 1024)>;
cache-sets = <512>;
cache-line-size = <256>;
cache-level = <3>;
};

serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
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14 changes: 14 additions & 0 deletions arch/arm/boot/dts/uniphier-ph1-sld3.dtsi
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Expand Up @@ -56,12 +56,14 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
next-level-cache = <&l2>;
};

cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
next-level-cache = <&l2>;
};
};

Expand Down Expand Up @@ -120,6 +122,18 @@
<0x20000100 0x100>;
};

l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
interrupts = <0 174 4>, <0 175 4>;
cache-unified;
cache-size = <(512 * 1024)>;
cache-sets = <256>;
cache-line-size = <128>;
cache-level = <2>;
};

serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
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13 changes: 13 additions & 0 deletions arch/arm/boot/dts/uniphier-ph1-sld8.dtsi
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Expand Up @@ -55,6 +55,7 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
next-level-cache = <&l2>;
};
};

Expand Down Expand Up @@ -91,6 +92,18 @@
#size-cells = <1>;
};

l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
interrupts = <0 174 4>, <0 175 4>;
cache-unified;
cache-size = <(256 * 1024)>;
cache-sets = <256>;
cache-line-size = <128>;
cache-level = <2>;
};

serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
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16 changes: 16 additions & 0 deletions arch/arm/boot/dts/uniphier-proxstream2.dtsi
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Expand Up @@ -56,24 +56,28 @@
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <0>;
next-level-cache = <&l2>;
};

cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <1>;
next-level-cache = <&l2>;
};

cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <2>;
next-level-cache = <&l2>;
};

cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a9";
reg = <3>;
next-level-cache = <&l2>;
};
};

Expand Down Expand Up @@ -110,6 +114,18 @@
#size-cells = <1>;
};

l2: l2-cache@500c0000 {
compatible = "socionext,uniphier-system-cache";
reg = <0x500c0000 0x2000>, <0x503c0100 0x4>,
<0x506c0000 0x400>;
interrupts = <0 174 4>, <0 175 4>, <0 190 4>, <0 191 4>;
cache-unified;
cache-size = <(1280 * 1024)>;
cache-sets = <512>;
cache-line-size = <128>;
cache-level = <2>;
};

serial0: serial@54006800 {
compatible = "socionext,uniphier-uart";
status = "disabled";
Expand Down

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