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Merge tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/g…
…it/arm/arm-soc
Pull ARM SoC platform updates from Olof Johansson:
"New and/or improved SoC support for this release:
Marvell Berlin:
- Enable standard DT-based cpufreq
- Add CPU hotplug support
Freescale:
- Ethernet init for i.MX7D
- Suspend/resume support for i.MX6UL
Allwinner:
- Support for R8 chipset (used on NTC's $9 C.H.I.P board)
Mediatek:
- SMP support for some platforms
Uniphier:
- L2 support
- Cleaned up SMP support, etc.
plus a handful of other patches around above functionality, and a few
other smaller changes"
* tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (42 commits)
ARM: uniphier: rework SMP operations to use trampoline code
ARM: uniphier: add outer cache support
Documentation: EXYNOS: Update bootloader interface on exynos542x
ARM: mvebu: add broken-idle option
ARM: orion5x: use mac_pton() helper
ARM: at91: pm: at91_pm_suspend_in_sram() must be 8-byte aligned
ARM: sunxi: Add R8 support
ARM: digicolor: select pinctrl/gpio driver
arm: berlin: add CPU hotplug support
arm: berlin: use non-self-cleared reset register to reset cpu
ARM: mediatek: add smp bringup code
ARM: mediatek: enable gpt6 on boot up to make arch timer working
soc: mediatek: Fix random hang up issue while kernel init
soc: ti: qmss: make acc queue support optional in the driver
soc: ti: add firmware file name as part of the driver
Documentation: dt: soc: Add description for knav qmss driver
ARM: S3C64XX: Use PWM lookup table for mach-smartq
ARM: S3C64XX: Use PWM lookup table for mach-hmt
ARM: S3C64XX: Use PWM lookup table for mach-crag6410
ARM: S3C64XX: Use PWM lookup table for smdk6410
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| Original file line number | Diff line number | Diff line change |
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| * Texas Instruments Keystone Navigator Queue Management SubSystem driver | ||
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| Driver source code path | ||
| drivers/soc/ti/knav_qmss.c | ||
| drivers/soc/ti/knav_qmss_acc.c | ||
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| The QMSS (Queue Manager Sub System) found on Keystone SOCs is one of | ||
| the main hardware sub system which forms the backbone of the Keystone | ||
| multi-core Navigator. QMSS consist of queue managers, packed-data structure | ||
| processors(PDSP), linking RAM, descriptor pools and infrastructure | ||
| Packet DMA. | ||
| The Queue Manager is a hardware module that is responsible for accelerating | ||
| management of the packet queues. Packets are queued/de-queued by writing or | ||
| reading descriptor address to a particular memory mapped location. The PDSPs | ||
| perform QMSS related functions like accumulation, QoS, or event management. | ||
| Linking RAM registers are used to link the descriptors which are stored in | ||
| descriptor RAM. Descriptor RAM is configurable as internal or external memory. | ||
| The QMSS driver manages the PDSP setups, linking RAM regions, | ||
| queue pool management (allocation, push, pop and notify) and descriptor | ||
| pool management. | ||
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| knav qmss driver provides a set of APIs to drivers to open/close qmss queues, | ||
| allocate descriptor pools, map the descriptors, push/pop to queues etc. For | ||
| details of the available APIs, please refers to include/linux/soc/ti/knav_qmss.h | ||
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| DT documentation is available at | ||
| Documentation/devicetree/bindings/soc/ti/keystone-navigator-qmss.txt | ||
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| Accumulator QMSS queues using PDSP firmware | ||
| ============================================ | ||
| The QMSS PDSP firmware support accumulator channel that can monitor a single | ||
| queue or multiple contiguous queues. drivers/soc/ti/knav_qmss_acc.c is the | ||
| driver that interface with the accumulator PDSP. This configures | ||
| accumulator channels defined in DTS (example in DT documentation) to monitor | ||
| 1 or 32 queues per channel. More description on the firmware is available in | ||
| CPPI/QMSS Low Level Driver document (docs/CPPI_QMSS_LLD_SDS.pdf) at | ||
| git://git.ti.com/keystone-rtos/qmss-lld.git | ||
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| k2_qmss_pdsp_acc48_k2_le_1_0_0_9.bin firmware supports upto 48 accumulator | ||
| channels. This firmware is available under ti-keystone folder of | ||
| firmware.git at | ||
| git://git.kernel.org/pub/scm/linux/kernel/git/firmware/linux-firmware.git | ||
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| To use copy the firmware image to lib/firmware folder of the initramfs or | ||
| ubifs file system and provide a sym link to k2_qmss_pdsp_acc48_k2_le_1_0_0_9.bin | ||
| in the file system and boot up the kernel. User would see | ||
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| "firmware file ks2_qmss_pdsp_acc48.bin downloaded for PDSP" | ||
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| in the boot up log if loading of firmware to PDSP is successful. | ||
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| Use of accumulated queues requires the firmware image to be present in the | ||
| file system. The driver doesn't acc queues to the supported queue range if | ||
| PDSP is not running in the SoC. The API call fails if there is a queue open | ||
| request to an acc queue and PDSP is not running. So make sure to copy firmware | ||
| to file system before using these queue types. |
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20 changes: 20 additions & 0 deletions
20
Documentation/devicetree/bindings/arm/mvebu-cpu-config.txt
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| MVEBU CPU Config registers | ||
| -------------------------- | ||
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| MVEBU (Marvell SOCs: Armada 370/XP) | ||
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| Required properties: | ||
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| - compatible: one of: | ||
| - "marvell,armada-370-cpu-config" | ||
| - "marvell,armada-xp-cpu-config" | ||
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| - reg: Should contain CPU config registers location and length, in | ||
| their per-CPU variant | ||
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| Example: | ||
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| cpu-config@21000 { | ||
| compatible = "marvell,armada-xp-cpu-config"; | ||
| reg = <0x21000 0x8>; | ||
| }; |
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60 changes: 60 additions & 0 deletions
60
Documentation/devicetree/bindings/arm/uniphier/cache-uniphier.txt
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| Original file line number | Diff line number | Diff line change |
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| UniPhier outer cache controller | ||
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| UniPhier SoCs are integrated with a full-custom outer cache controller system. | ||
| All of them have a level 2 cache controller, and some have a level 3 cache | ||
| controller as well. | ||
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| Required properties: | ||
| - compatible: should be "socionext,uniphier-system-cache" | ||
| - reg: offsets and lengths of the register sets for the device. It should | ||
| contain 3 regions: control register, revision register, operation register, | ||
| in this order. | ||
| - cache-unified: specifies the cache is a unified cache. | ||
| - cache-size: specifies the size in bytes of the cache | ||
| - cache-sets: specifies the number of associativity sets of the cache | ||
| - cache-line-size: specifies the line size in bytes | ||
| - cache-level: specifies the level in the cache hierarchy. The value should | ||
| be 2 for L2 cache, 3 for L3 cache, etc. | ||
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| Optional properties: | ||
| - next-level-cache: phandle to the next level cache if present. The next level | ||
| cache should be also compatible with "socionext,uniphier-system-cache". | ||
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| The L2 cache must exist to use the L3 cache; the cache hierarchy must be | ||
| indicated correctly with "next-level-cache" properties. | ||
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| Example 1 (system with L2): | ||
| l2: l2-cache@500c0000 { | ||
| compatible = "socionext,uniphier-system-cache"; | ||
| reg = <0x500c0000 0x2000>, <0x503c0100 0x4>, | ||
| <0x506c0000 0x400>; | ||
| cache-unified; | ||
| cache-size = <0x80000>; | ||
| cache-sets = <256>; | ||
| cache-line-size = <128>; | ||
| cache-level = <2>; | ||
| }; | ||
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| Example 2 (system with L2 and L3): | ||
| l2: l2-cache@500c0000 { | ||
| compatible = "socionext,uniphier-system-cache"; | ||
| reg = <0x500c0000 0x2000>, <0x503c0100 0x8>, | ||
| <0x506c0000 0x400>; | ||
| cache-unified; | ||
| cache-size = <0x200000>; | ||
| cache-sets = <512>; | ||
| cache-line-size = <128>; | ||
| cache-level = <2>; | ||
| next-level-cache = <&l3>; | ||
| }; | ||
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| l3: l3-cache@500c8000 { | ||
| compatible = "socionext,uniphier-system-cache"; | ||
| reg = <0x500c8000 0x2000>, <0x503c8100 0x8>, | ||
| <0x506c8000 0x400>; | ||
| cache-unified; | ||
| cache-size = <0x400000>; | ||
| cache-sets = <512>; | ||
| cache-line-size = <256>; | ||
| cache-level = <3>; | ||
| }; |
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| Original file line number | Diff line number | Diff line change |
|---|---|---|
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|
@@ -920,7 +920,7 @@ M: Tsahee Zidenberg <[email protected]> | |
| S: Maintained | ||
| F: arch/arm/mach-alpine/ | ||
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| ARM/ATMEL AT91RM9200 AND AT91SAM ARM ARCHITECTURES | ||
| ARM/ATMEL AT91RM9200, AT91SAM9 AND SAMA5 SOC SUPPORT | ||
| M: Nicolas Ferre <[email protected]> | ||
| M: Alexandre Belloni <[email protected]> | ||
| M: Jean-Christophe Plagniol-Villard <[email protected]> | ||
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@@ -1630,7 +1630,9 @@ M: Masahiro Yamada <[email protected]> | |
| L: [email protected] (moderated for non-subscribers) | ||
| S: Maintained | ||
| F: arch/arm/boot/dts/uniphier* | ||
| F: arch/arm/include/asm/hardware/cache-uniphier.h | ||
| F: arch/arm/mach-uniphier/ | ||
| F: arch/arm/mm/cache-uniphier.c | ||
| F: drivers/i2c/busses/i2c-uniphier* | ||
| F: drivers/pinctrl/uniphier/ | ||
| F: drivers/tty/serial/8250/8250_uniphier.c | ||
|
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||
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| Original file line number | Diff line number | Diff line change |
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| @@ -0,0 +1,46 @@ | ||
| /* | ||
| * Copyright (C) 2015 Masahiro Yamada <[email protected]> | ||
| * | ||
| * This program is free software; you can redistribute it and/or modify | ||
| * it under the terms of the GNU General Public License as published by | ||
| * the Free Software Foundation; either version 2 of the License, or | ||
| * (at your option) any later version. | ||
| * | ||
| * This program is distributed in the hope that it will be useful, | ||
| * but WITHOUT ANY WARRANTY; without even the implied warranty of | ||
| * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | ||
| * GNU General Public License for more details. | ||
| */ | ||
|
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| #ifndef __CACHE_UNIPHIER_H | ||
| #define __CACHE_UNIPHIER_H | ||
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| #include <linux/types.h> | ||
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| #ifdef CONFIG_CACHE_UNIPHIER | ||
| int uniphier_cache_init(void); | ||
| int uniphier_cache_l2_is_enabled(void); | ||
| void uniphier_cache_l2_touch_range(unsigned long start, unsigned long end); | ||
| void uniphier_cache_l2_set_locked_ways(u32 way_mask); | ||
| #else | ||
| static inline int uniphier_cache_init(void) | ||
| { | ||
| return -ENODEV; | ||
| } | ||
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| static inline int uniphier_cache_l2_is_enabled(void) | ||
| { | ||
| return 0; | ||
| } | ||
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| static inline void uniphier_cache_l2_touch_range(unsigned long start, | ||
| unsigned long end) | ||
| { | ||
| } | ||
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| static inline void uniphier_cache_l2_set_locked_ways(u32 way_mask) | ||
| { | ||
| } | ||
| #endif | ||
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| #endif /* __CACHE_UNIPHIER_H */ |
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