Significant change to RISC V and scalable vector code generation. #7616
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added 3 commits
June 5, 2023 07:01
issues iwth single element vectors being confused with scalars and other conversions that can happen via using call_intrin. Allows using any size vector. Only downside is splitting large vectors no longer happens, but RISC-V allows an LMUL of 8, meaning a vector of up to 8 times the vector register size will compile so this is much less of an issue. Splitting larger vectors can be added. Should also allow fractionaly LMUL in all cases, but this is not verified.
support. Should handle many more cases and be well on the way to handling arbitary vector widths within the LMUL range. More tests added to simd_op_check_riscv . Likely well setup to move SVE2 to a similar approach, perhaps without the full genearilty on vector lengths. (I.e. they may need to be quantized to vscale, or offer better performance in that case.)
…/halide/Halide into riscv_intrinsics_single_lane_fix
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Looks like some legitimate failures, e.g. https://buildbot.halide-lang.org/master/#/builders/84/builds/40 |
was being presented with a scalar only mismatch. Changed it to ignore scalar to scalar cases.) Address review feedback.
…/halide/Halide into riscv_intrinsics_single_lane_fix
steven-johnson
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Jun 7, 2023
ardier
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Mar 3, 2024
…lide#7616) * Completely rework how RISC-V vector intrinsics are called to avoid issues iwth single element vectors being confused with scalars and other conversions that can happen via using call_intrin. Allows using any size vector. Only downside is splitting large vectors no longer happens, but RISC-V allows an LMUL of 8, meaning a vector of up to 8 times the vector register size will compile so this is much less of an issue. Splitting larger vectors can be added. Should also allow fractionaly LMUL in all cases, but this is not verified. * Significant refactor/rewrite of RISC V vector intrinsics support. Should handle many more cases and be well on the way to handling arbitary vector widths within the LMUL range. More tests added to simd_op_check_riscv . Likely well setup to move SVE2 to a similar approach, perhaps without the full genearilty on vector lengths. (I.e. they may need to be quantized to vscale, or offer better performance in that case.) * Formatting fixes. * More formatting. * Don't try to convert void types to match expected vector type. * Backout comment change that is no longer relevant. * Fix failure in camera_pipe app. (Code to make sure vector types match was being presented with a scalar only mismatch. Changed it to ignore scalar to scalar cases.) Address review feedback. * One more review comment. * Comment fix. --------- Co-authored-by: Steven Johnson <[email protected]>
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It is now possible to convert between fixed and scalable vectors in LLVM. Full generality is likely not working and various architecture specific intrinsics still require scalable vectors. This PR moves to using fixed vectors to represent types that are not quantized to a vscale size and converting to a longer vscale size as necessary.
RISC V vectorization should support lengths from 2 lanes up to 8 times the number of lanes supported for the given type and vector_bits specified in the target. (All the LMUL values.) 1 lane vectors likely do not work for intrinsics quite yet due to confusion re: scalars, but this PR should remove this case showing up via just doing scalar operations when scalars are involved. (Vector/scalar is supported, and some test cases were added. More coverage for .vi vs .vx forms is needed.)
PR will likely need some changed but want to get review started now.