This branch contains the DMT transmit test and demonstation system. The system overview is presented below:
- PL Scrambler
- PL signaling/pilot insertion
- Dummy frame insertion
- Integrate code from BB filter/quadrature modulation and from DVB FPGA
-
Vivado project setup for ZC706 board
- Zynq DMA setup for PS -> PL transfer
- AXI Lite / Stream routing structure
- Create RTL module from AD's JESD204B code which be instantiated to the PL top level - Note: AD's github repo might have some of this already
-
PS Linux setup
- Initial bring-up
- DMA driver test
- Integrate AD's AD9361 C configuration library
- All ORI West Lab PC parts ordered
- All ORI West Lab PC parts received
- ORI West Lab PC parts shipped 2 April 2021 (Two dead hard drives, broken glass door of case)
- ORI West Lab PC parts received 9 April 2021
- ORI West Lab PC built 5 May 2021 (Unraid tuning in process)
- DVB-S2X commercial gear recognized in ORI West Lab PC
- DVB-S2X commercial gear tested in ORI West Lab PC
- Configure commercial DVB-S2X demodulator for demo verification
- Add
phase4ground/dvb_fpga
as Git submodule