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v4: D2 reversal + fact-bundle reseed plan (RATIFIED 2026-05-17) - #3223
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v4 #3223: machine_code/Verilog register width is a structural Witness, not a comment (openai-pro RC)
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v4 #3223: LLVM example — add i32 is signedness-neutral, can't supply signed Int32 (openai-pro 13433)
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