R3 Substrate: IntPlatform/UIntPlatform + isize/usize Rust rows

dsl/std/integer.dag

@@ -45,6 +45,7 @@ module std.integer
 import std.algebra { OrderedRing, Semiring, AbelianGroup, GroupCompletion }
 import std.bit { Byte, Word16, Word32, Word64, Word128 }
 import std.nat { Nat }
+import std.machine_constraints { Compose, MachineWidth, PointerWidth }
 
 // Signed integers: ordered rings (add + negate + mul + compare)
 type Int8 = OrderedRing<Byte>
@@ -110,6 +111,37 @@ type UInt128 = Semiring<Word128>
 type Int = AbelianGroup<GroupCompletion<Nat>>
 type UInt = Nat
 
+// IntPlatform / UIntPlatform — pointer-width-sized integer substrate concepts.
+//
+// Per Director Q1+Q2+Q3+Q4 RATIFIED at gunbc#1739 #issuecomment-4393248961
+// (2026-05-07) + inner-token rename `Platform` → `PointerWidth` RATIFIED
+// at gunbc#828 #issuecomment-4393616097. Outer carrier names
+// `IntPlatform`/`UIntPlatform` stay verbatim (Q1 RATIFIED). Inner substrate
+// token is `PointerWidth` to avoid collision with pre-existing
+// `Platform = Linux | Macos | Windows` (OS-identity axis) at
+// `dsl/std/types.dag:356`; per `feedback_reason_not_label`, pointer-width
+// is the structural reason and OS-identity vs pointer-width are
+// orthogonal axes (32-bit Linux vs 64-bit Linux are different pointer
+// widths but same OS).
+//
+// Composition per Q-MachineConstraint-Carrier sub-decision 3
+// (gunbc#828 #issuecomment-4385530115) extended with substrate token
+// `PointerWidth` per Q3 ratification (substrate-concept layer, NOT target-
+// only) — `MachineWidth<PointerWidth>` resolves at Grounding-emit time
+// per target spec; substrate stays target-agnostic.
+//
+// Direct-consumer site: `src/v3/spec/rust.dag` `TargetIntegerTypeInhabitance`
+// rows for `isize` (kernel_integer = IntPlatform) and `usize`
+// (kernel_integer = UIntPlatform) with `bound: PlatformDependentFact`.
+// Targets without native pointer-sized integers (Python's arbitrary-
+// precision `int`, etc.) handle ground-time projection via target-
+// conditioned **lowering** — substrate stays clean (Grounding-lane work).
+//
+// Practice 4: N/A — type aliases over existing `Compose<...>` carrier;
+// no new sum types or coproducts introduced here.
+type IntPlatform  = Compose<Int,  MachineWidth<PointerWidth>>
+type UIntPlatform = Compose<UInt, MachineWidth<PointerWidth>>
+
 // Nat-alignment refinements (S9 Slice 2 / Slice 2.5 / Phase-4).
 //
 // NonNegativeInt formerly lived in dsl/std/types.dag refining Int with a

dsl/std/machine_constraints.dag

@@ -44,6 +44,55 @@ module std.machine_constraints
 //   `Nat` carrier — then delete this block and re-measure consumers.
 type MachineWidth<bits>
 
+// ----------------------------------------------------------------------------
+// PointerWidth — substrate token for target-resolved pointer-width axis.
+// ----------------------------------------------------------------------------
+//
+// Per Director Q1+Q2+Q3+Q4 RATIFIED at gunbc#1739 #issuecomment-4393248961
+// (2026-05-07) + inner-token rename `Platform` → `PointerWidth` RATIFIED at
+// gunbc#828 #issuecomment-4393616097 (per `feedback_reason_not_label` —
+// pointer-width is the structural reason; the original brief framing
+// collided with pre-existing `Platform = Linux | Macos | Windows` at
+// `dsl/std/types.dag:356`, which is the OS-identity axis, NOT the pointer-
+// width axis; conflating them would lose orthogonality).
+//
+// `PointerWidth` names the target-resolved pointer-width axis at substrate-
+// concept layer (NOT target-only) per `feedback_target_agnostic_ir`:
+// multiple targets carry pointer-sized integers (Rust `isize`/`usize`, Go
+// `int`/`uint`, C `intptr_t`, …); modeling at substrate-concept layer keeps
+// substrate target-agnostic and lets Grounding project to specific widths
+// at emit time.
+//
+// **Shape: opaque token** (Option β per worker-DFS at dispatch). Sibling to
+// the phantom-`bits` parameter on `MachineWidth<bits>`: where `bits = 32`
+// resolves at substrate-load time (literal `Nat` index), `bits = PointerWidth`
+// resolves at Grounding-emit time (target-conditioned width). No payload at
+// the substrate-concept layer — Grounding consumers project `PointerWidth`
+// to the per-target width (Rust pointer-width 32/64, Go `int` width, etc.).
+//
+// Practice 4 dissolution ledger (nominal opaque carrier; no coproduct variants):
+// - Pattern 1 (fact placement): fails — `PointerWidth` centralizes the
+//   "target-resolved pointer-width" axis; one slot per use, not multiple
+//   competing slots.
+// - Pattern 2 (variant-is-data): n/a — no variants.
+// - Pattern 3 (algebraic form): fails — `PointerWidth` is a target-
+//   resolution tag, not an algebraic operation over widths.
+// - Pattern 4 (dimensional): fails — target-resolved pointer-width is an
+//   irreducible substrate fact at this layer; per-target enumeration is
+//   Grounding's job (concrete width 32 / 64 etc. lands at emit time).
+// Verdict: terminal at substrate-concept layer.
+//
+// CONSTRAINED-INHABITANCE GAP (mirrors `MachineWidth<bits>`'s P2/P5 scaffold):
+//   Same parser-parallel constraint posture — `PointerWidth` is consumed as
+//   a `MachineWidth<PointerWidth>` argument; mechanical width-projection
+//   is Grounding's enforcement. No structural `PointerWidth : Nat` bound
+//   at parse time (substrate grammar gap).
+//
+//   **Dissolution trigger:** when substrate grammar admits bounded type-
+//   level parameters (the same trigger named on `MachineWidth<bits>` above),
+//   tighten `PointerWidth`'s constraint surface alongside.
+type PointerWidth
+
 // ----------------------------------------------------------------------------
 // Compose<Algebra, MachineConstraint> — type-level phantom composition (ratified interaction shape).
 // ----------------------------------------------------------------------------