Domain stream: the EBM Langevin loop through the MLIR/LLVM backbone — CPU JIT and one cooperative kernel on gfx1151/gfx1201/sm_120 (W4-PRODUCT-1 / AD-SOLVER-IFT-1)

CLAUDE.md

@@ -56,7 +56,7 @@ x86 AMX/AVX512, Apple M-series CPU/GPU.
 
 **Execution reality (updated 2026-09-15):** the **x86 AVX-512** backend and
 **Apple CPU (Accelerate) + GPU (MPS/MSL/MPSGraph + Metal 4 MPP `matmul2d`)**
-backends execute natively. **ROCm** executes on two RDNA parts: **gfx1151**
+backends execute natively. Since 2026-09-16 the EBM Langevin loop's compiler-derived gradient runs *inside* one cooperative kernel on gfx1151, gfx1201 and sm_120 through the row-program emitter (`tessera-row-program-to-gpu`), bit-exact with the CPU JIT lane's policy — a correctness lane, not a promotion. **ROCm** executes on two RDNA parts: **gfx1151**
 (Strix Halo, RDNA 3.5, `Princess-Luna`) has broad native execution across the
 attention family, norms/activations, matmul compositions, MoE transport, SSM,
 EBM and warp-shuffle lanes; **gfx1201** (RX 9070 XT, RDNA4, `Tajasarus`, added
@@ -434,6 +434,23 @@ Per-phase deliverables and the open-work priority queue live in
     falsifier" clause above is history. Route MLIR promise/contract claims to
     Tajasarus (or any assertions build) before recording "does not reproduce".
 
+    **Third instance (2026-09-16): the EBM row-program chain ran green on every
+    NDEBUG driver in the fleet and aborted twice on Tajasarus's assertions-ON
+    driver** — `--inline` builds its interface collection over every loaded
+    dialect and the LLVM dialect *promises* a `DialectInlinerInterface` that
+    `registerAllExtensions` does not provide (`tessera-opt` now calls
+    `LLVM::registerInlinerInterface`), and a pass that parses a textual
+    skeleton naming `tile.alloc_shared` had not declared the tile dialect in
+    `getDependentDialects` ("Loading a dialect (tile) while in a
+    multi-threaded execution context"), nor the Tessera dialect its
+    `tessera.*` provenance attributes load. All one-line fixes; all invisible
+    without that box. (Separately, sm_120 showed the NVVM arena route's
+    `math.sqrt` reaches libdevice's *approximate* `__nv_sqrtf` because MLIR
+    never sets the precise-sqrt reflect flag, and `convert-gpu-to-nvvm`
+    outlaws `llvm.intr.sqrt` — call libdevice's rounding-explicit
+    `__nv_fsqrt_rn` when a result must be IEEE; `docs/audit/backend/nvidia/todo.md`.) Run every new pass through Tajasarus before recording
+    "passes" (sync `EBM-NATIVE-GPU-2026-09-16`).
+
     **Separately, still open: `TileToX86Pass` loads `tessera_x86` from inside
     `runOnOperation()`** (`src/transforms/lib/TileToX86Pass.cpp:1045`, a by-name
     `getOrLoadDialect` used to avoid linking the optional backend). MLIR forbids
@@ -932,9 +949,13 @@ ninja -C build tessera-opt        # 32 threads; ~1-2 min cold
 # Since 2026-09-16 the Clifford backend is also what puts the geometric-algebra
 # lane into libtessera_jit (tessera_jit_has_clifford()) and builds
 # ts-clifford-opt, which the native GPU route (native_clifford_gpu.py) shells
-# out to; every WSL box's `build/` (Princess-Luna, Super-Bear, Tajasarus) and
-# the Mac configure it ON, so domain fixtures and the GA lanes are
-# fleet-covered, not Mac-only.
+# out to, and the EBM backend puts the energy lane in (tessera_jit_has_ebm();
+# paired autodiff + tessera-ebm-lower-langevin). Every WSL box's `build/`
+# (Princess-Luna, Super-Bear, Tajasarus, plus Tajasarus's build-assertions)
+# and the Mac configure both ON, so domain fixtures and the GA/EBM lanes are
+# fleet-covered, not Mac-only. bf16 JIT tests fail on Super-Bear (Zen 2 has
+# no AVX512-BF16; unresolved `_mlir_ciface_*` symbols) independent of any
+# branch — bf16 JIT proof belongs on the Zen 5 hosts.
 cmake -S . -B build -G Ninja -DTESSERA_BUILD_EBM_BACKEND=ON -DTESSERA_BUILD_CLIFFORD_BACKEND=ON
 
 # Re-verify a C++ pass change end-to-end: rebuild → lit fixture + FileCheck → drift test

benchmarks/baselines/ebm_langevin_native_gpu_20260916/README.md

@@ -0,0 +1,44 @@
+# The EBM Langevin loop as one cooperative kernel, on the owning devices
+
+Owner: W4-PRODUCT-1 / AD-SOLVER-IFT-1 (sync `EBM-NATIVE-GPU-2026-09-16`).
+`record_ebm_langevin_native_gpu.py` executed independently on three owning
+devices; `source-hashes.json` binds the implementation. Packets are
+correctness evidence; no performance is measured or claimed, and gfx1151 /
+gfx1201 / sm_120 proofs never transfer.
+
+| Packet | Host | Device | Rows | Worst abs error |
+|---|---|---|---|---|
+| `rocm_gfx1151.json` | Princess-Luna (WSL2, ROCm 10.0) | gfx1151 | 6 | 0 |
+| `rocm_gfx1201.json` | Tajasarus (WSL2, ROCm 10.0, `TESSERA_ROCM_CHIP=gfx1201`, assertions-ON driver) | gfx1201 | 6 | 0 |
+| `nvidia_sm120.json` | The-Super-Bear (WSL2, CUDA 13.4 / driver 610.88) | sm_120 (RTX 5070) | 6 | 0 |
+
+Each row is one K-step loop over the quadratic energy `0.5·Σ(x − y)²` at one
+`(shape, K, T)` — `(4×8, 1, 0.7)`, `(6×8, 5, 0.7)`, `(3×5, 12, 0.7)`,
+`(9×100, 4, 0.3)`, `(16×33, 8, 0)`, `(2×1024, 3, 0.5)` — compared with
+`native_langevin.reference_langevin_loop`, the numpy statement of the declared
+Philox-4x32-10 / Box–Muller policy, and the returned key. `kernel_structure`
+is read from the arena IR of the packaged kernel: one `gpu.func`, one
+`scf.for` carrying `(state f32, key i64)` in registers (the loop-invariant key
+word is hoisted by canonicalization), 18 `arith.mului_extended` Philox rounds
+inside the loop, no barrier (the quadratic gradient is elementwise), and no
+`linalg`/`tensor` op left.
+
+How the kernel is produced (no Python-emitted arithmetic): one `tessera-opt`
+invocation runs `--tessera-autodiff-paired` (the gradient),
+`--tessera-ebm-canonicalize --tessera-ebm-lower-langevin` (the step with the
+noise), `--tessera-to-linalg --inline --convert-elementwise-to-linalg
+--canonicalize --cse` (a `[rows, features]` row program in linalg) and
+`--tessera-row-program-to-gpu` (one block per row, one lane per feature,
+the K-step loop in registers, ordered shared-memory reductions); the tensor
+contract is attached, `build_native_gpu_storage` packages it and the native
+storage binding launches it. The emitter's reduction path is exercised by the
+row-normalization device test in `tests/unit/test_ebm_native_langevin_gpu.py`
+(bit-exact with the sequential f32 fold on the same three devices), not by
+these rows.
+
+Reproduce on an owning host (EBM backend configured ON, toolkit env sourced):
+
+```bash
+PYTHONPATH=python:. python benchmarks/record_ebm_langevin_native_gpu.py --backend rocm --chip gfx1151 \
+  --compiler build/tools/tessera-opt/tessera-opt --output <dir>/rocm_gfx1151.json
+```

benchmarks/baselines/ebm_langevin_native_gpu_20260916/nvidia_sm120.json

@@ -0,0 +1,114 @@
+{
+  "schema": 1,
+  "backend": "nvidia",
+  "chip": "sm_120",
+  "host": "The-Super-Bear",
+  "compiler_sha256": "7715c2cae3b62acda99052651b84eaeaa73b3ad317deaa0a2586af07ef6543f9",
+  "llvm_bin": "/usr/lib/llvm-23/bin",
+  "recorder_sha256": "8d1a24427a4d9a8395aaffa4b6a4c2c69c0c983008dd0a6d54b851142c508ced",
+  "rows": [
+    {
+      "shape": [
+        4,
+        8
+      ],
+      "steps": 1,
+      "temperature": 0.7,
+      "max_abs_error": 0.0,
+      "next_key": [
+        20017429977207,
+        43
+      ],
+      "binding": "ff3f26a07d47eb4b4791c6db506488898dfb84f45f9c3b317910b7ce79858157"
+    },
+    {
+      "shape": [
+        6,
+        8
+      ],
+      "steps": 5,
+      "temperature": 0.7,
+      "max_abs_error": 0.0,
+      "next_key": [
+        20017429977211,
+        47
+      ],
+      "binding": "7f8adc6b089de3ff02502af88e2c6c87e062e2291e3acd23826e37877e9f6e5c"
+    },
+    {
+      "shape": [
+        3,
+        5
+      ],
+      "steps": 12,
+      "temperature": 0.7,
+      "max_abs_error": 0.0,
+      "next_key": [
+        20017429977218,
+        54
+      ],
+      "binding": "c4d03d8d12909999d1a181b0cd6602bfb228f2e54382fac0e7ccfc15bc2ec15c"
+    },
+    {
+      "shape": [
+        9,
+        100
+      ],
+      "steps": 4,
+      "temperature": 0.3,
+      "max_abs_error": 0.0,
+      "next_key": [
+        20017429977210,
+        46
+      ],
+      "binding": "82184df27e9b8e926c06630d60c2692044cabd96681cb71f7847e68340705d36"
+    },
+    {
+      "shape": [
+        16,
+        33
+      ],
+      "steps": 8,
+      "temperature": 0.0,
+      "max_abs_error": 0.0,
+      "next_key": [
+        20017429977214,
+        50
+      ],
+      "binding": "dee9be1aac695b75ad94620852cf7b1e9ef85b0a6ae417b3f26b67e415a85d6f"
+    },
+    {
+      "shape": [
+        2,
+        1024
+      ],
+      "steps": 3,
+      "temperature": 0.5,
+      "max_abs_error": 0.0,
+      "next_key": [
+        20017429977209,
+        45
+      ],
+      "binding": "85a7eb9f04b41abc4e2a1cd4a608e36b25bd498d2630e393659075e25374df3b"
+    }
+  ],
+  "kernel_structure": {
+    "gpu_funcs": 1,
+    "loops": 1,
+    "loop_carried": [
+      "f32, i64"
+    ],
+    "philox_mul": 18,
+    "barriers": 0,
+    "linalg_or_tensor_ops": 0
+  },
+  "proofs": [
+    "the K-step loop is one device launch, bit-exact with the declared Philox/Box-Muller policy for every case (K in 1..12, F in 5..1024, T in {0, 0.3, 0.5, 0.7})",
+    "the gradient is the paired autodiff pass's own adjoint, lowered inside the kernel (no host gradient, no host noise, no Python-emitted kernel)",
+    "one gpu.func, one scf.for carrying (state, key, key) in registers, Philox inside the loop"
+  ],
+  "promotion_eligible": false,
+  "measured_performance": false,
+  "envelope": "f32, quadratic energy, [rows, features] with features <= 1024; per-call host transfers; correctness only",
+  "rocm_chip_env": null
+}

benchmarks/baselines/ebm_langevin_native_gpu_20260916/rocm_gfx1151.json

@@ -0,0 +1,114 @@
+{
+  "schema": 1,
+  "backend": "rocm",
+  "chip": "gfx1151",
+  "host": "Princess-Luna",
+  "compiler_sha256": "a68c821632fa74eca218d2519a58a6749c4dba7580335d52cbe7d29dcd0c1949",
+  "llvm_bin": "/usr/lib/llvm-23/bin",
+  "recorder_sha256": "8d1a24427a4d9a8395aaffa4b6a4c2c69c0c983008dd0a6d54b851142c508ced",
+  "rows": [
+    {
+      "shape": [
+        4,
+        8
+      ],
+      "steps": 1,
+      "temperature": 0.7,
+      "max_abs_error": 0.0,
+      "next_key": [
+        20017429977207,
+        43
+      ],
+      "binding": "abc46be93febf94155207757e2bc85fc641b8e02723d6e84c98ede2900c579d2"
+    },
+    {
+      "shape": [
+        6,
+        8
+      ],
+      "steps": 5,
+      "temperature": 0.7,
+      "max_abs_error": 0.0,
+      "next_key": [
+        20017429977211,
+        47
+      ],
+      "binding": "80b884cb338c99a51930415b2f9553e5e5eff7a7d9b08eb88ef7c5a9909aeff3"
+    },
+    {
+      "shape": [
+        3,
+        5
+      ],
+      "steps": 12,
+      "temperature": 0.7,
+      "max_abs_error": 0.0,
+      "next_key": [
+        20017429977218,
+        54
+      ],
+      "binding": "94dd26cd5e765ce817148e7f4957ef8e53da876710d6dd9e3fd9db08a438cfba"
+    },
+    {
+      "shape": [
+        9,
+        100
+      ],
+      "steps": 4,
+      "temperature": 0.3,
+      "max_abs_error": 0.0,
+      "next_key": [
+        20017429977210,
+        46
+      ],
+      "binding": "d41479668d50b16cb233347b6d692e5c97cedfd389c96ecea4a6920b0b49f81d"
+    },
+    {
+      "shape": [
+        16,
+        33
+      ],
+      "steps": 8,
+      "temperature": 0.0,
+      "max_abs_error": 0.0,
+      "next_key": [
+        20017429977214,
+        50
+      ],
+      "binding": "8881cc2b4a96b206b5d6ec9875603fd9f436f46f963bc2c53469d6805344493e"
+    },
+    {
+      "shape": [
+        2,
+        1024
+      ],
+      "steps": 3,
+      "temperature": 0.5,
+      "max_abs_error": 0.0,
+      "next_key": [
+        20017429977209,
+        45
+      ],
+      "binding": "be4fe83e60ca9158b5f817d68f5a555afeeb949b79d9f57598393f9b21b62d0b"
+    }
+  ],
+  "kernel_structure": {
+    "gpu_funcs": 1,
+    "loops": 1,
+    "loop_carried": [
+      "f32, i64"
+    ],
+    "philox_mul": 18,
+    "barriers": 0,
+    "linalg_or_tensor_ops": 0
+  },
+  "proofs": [
+    "the K-step loop is one device launch, bit-exact with the declared Philox/Box-Muller policy for every case (K in 1..12, F in 5..1024, T in {0, 0.3, 0.5, 0.7})",
+    "the gradient is the paired autodiff pass's own adjoint, lowered inside the kernel (no host gradient, no host noise, no Python-emitted kernel)",
+    "one gpu.func, one scf.for carrying (state, key, key) in registers, Philox inside the loop"
+  ],
+  "promotion_eligible": false,
+  "measured_performance": false,
+  "envelope": "f32, quadratic energy, [rows, features] with features <= 1024; per-call host transfers; correctness only",
+  "rocm_chip_env": null
+}