rocm/gfx1151: K-unroll WMMA GEMM lever — measured, regresses, kept as reference - #357
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… reference The occupancy/dual-issue follow-up. Rigorously swept the two remaining WMMA GEMM levers on-device; both are negative, closing the lever. - Asymmetric-tile sweep (2x3,3x3,4x2,2x5,5x2,5x3,3x5,2x6,6x2,2x7,2x8,3x6 at 1024-4096³): no untested tile beats the 2x4/3x4 adaptive. 3x4 is the confirmed sweet spot; 4x3 edges it ~3% at 4096³ only. The 12-tile register-budget sweet spot holds. - K-unroll (new kKernelTemplateKU: KU 16-wide K-panels/step then KU*MT*NT WMMAs; ..._bench_ku / ..._ku C-ABI + timedKernelLaunches/runDeviceGemm paths): REGRESSES. KU2 -54..-66% on 3x4, -43..-49% on 4x3; KU4 collapses -60..-71%. The KUx a/b load buffers blow the VGPR budget → occupancy collapse (same cliff as 4x4). Only 2x4-KU2 at 4096³ is +2%, still far below 3x4-KU1. Verified correct (test_rocm_gemm_ku_reference.py, incl. ragged-K tail + KU=2/4); kept as a correctness-verified REFERENCE rung (like the LDS/pipe rungs) for a lower-register design or a datacenter arch — NOT promoted (production stays the size-adaptive 2x4/3x4 register kernel). STRIX_HALO Stage H documents the sweep + the synthesis: every register-pressure lever hits the occupancy cliff, every memory-hierarchy lever is a wash on this unified-memory APU, and dual-issue does not apply to a WMMA-issue-bound loop (VOPD pairs VALU, not WMMA). The kernel is at the practical ceiling (~13 TFLOP/s ≈ 22% peak) for this design on Strix Halo. Verified: ruff + mypy clean; 50-test sweep green. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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…CI/review)
- CI drift: the new tessera_rocm_wmma_gemm_f16_{bench_ku,ku} C-ABI symbols are
scanned into runtime_abi.csv; regenerate runtime_abi + compiler_progress.
- Review (P2): runGemmKU validated only M/N/K, so a nonpositive tile reached
gridFor (mt/nt==0 → div-by-zero) or the kernel (ku==0 → K-loop increments by 0
→ GPU hang). Reject mt/nt/ku <= 0 before compile/launch (mirrors benchVariantKU)
+ reject tests.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
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The occupancy/dual-issue follow-up from PR #356's inventory §9. I rigorously swept the two remaining WMMA GEMM levers on-device — both are negative, which closes the lever with data (and saves future effort chasing it).
What I measured (gfx1151, kernel-only, best-of-N)
1. Every untested asymmetric macro-tile (2×3, 3×3, 4×2, 2×5, 5×2, 5×3, 3×5, 2×6, 6×2, 2×7, 2×8, 3×6) at 1024–4096³:
No untested tile beats the current 2×4/3×4 adaptive. 3×4 is the confirmed sweet spot 1024–3072³; 4×3 edges it by only ~3% at 4096³ (a wash at 3072³). The 12-tile register-budget sweet spot holds.
2. K-unrolling (new
kKernelTemplateKU— KU 16-wide K-panels/step → more MLP, then KU·MT·NT WMMAs):Regresses. The KU× a/b load buffers blow the VGPR budget → occupancy collapse — the same cliff as 4×4. Only 2×4-KU2 at 4096³ is +2%, still far below 3×4-KU1.
Synthesis
Every lever that adds register pressure (bigger tiles, K-unroll, register prefetch) hits the same occupancy cliff; every memory-hierarchy lever (LDS, pipelined LDS) is a wash on unified LPDDR5x (Stage F). And the named dual-issue lever doesn't apply — the inner loop is WMMA-issue-bound (12 back-to-back WMMAs/step) and RDNA3 VOPD pairs VALU ops, not WMMA. The production register kernel is at the practical ceiling for this design on Strix Halo (~13 TFLOP/s ≈ 22% of the ~59 f16 WMMA peak). Past here needs a fundamentally lower-register-footprint design, or a datacenter arch where global bandwidth is the bottleneck and the kept LDS/pipe/KU rungs pay off.
What's kept
The KU variant +
..._bench_ku/..._kuC-ABI entries are retained as a correctness-verified reference rung (like the existing LDS/pipe rungs), NOT promoted — production stays the size-adaptive 2×4/3×4 register kernel.test_rocm_gemm_ku_reference.pylocks correctness across shapes (incl. ragged-K tail + KU=2/4). STRIX_HALO Stage H documents the full sweep + synthesis.Verification
ruff + mypy clean; 50-test sweep green (KU reference, f32 gemm, perf ratchet, WMMA runtime symbol).
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