docs: reconcile status surfaces with the merged C/D/E backend wave - #303
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#286–#302) The plan doc carried "landed" annotations for Workstreams C/D/E, but the all-up status surfaces had drifted behind. Refresh them (prose only; counts stay in the generated dashboards per Decision #26): - MASTER_AUDIT.md: frontmatter + body date → 2026-07-07; added a 2026-07-07 reconcile banner (A–E spine wave); refreshed the NVIDIA (Phase G) row — no longer "one op × one arch": now a generic CUDA lane over all four fusable region kinds + hand-emitted tensor-core mma.sync GEMM/flash-attn Tier-2 lanes the arbiter selects, via a shipped PTX launch bridge, all F4-gated and hardware-proven; updated the Runtime/backend + ROCm rows to note the generic plugin lanes + arbiter + x86 Zen 5 execution. - backend/nvidia/NVIDIA_AUDIT.md: frontmatter date → 2026-07-07 (body was already reconciled in #298). - COMPILER_REFACTOR_PLAN.md: the stale Phase-0 E3 row (⬜⬜⬜) → landed (E3 escape hatch lives in the D1 `force` path + PR #298 test); added the E3-landed annotation to the bullet. - README.md: refreshed the NVIDIA support-snapshot row; reframed "Where the compiler is going" from future-direction to largely-built (the three-tier framework + arbiter now live in python/tessera/compiler/emit/, NVIDIA/ROCm/x86 executing). - docs/README.md: same north-star reframe + a new NVIDIA sm_120 executing-lane status row. Doc-only. Frontmatter contract 8/8, generated-doc drift gate in sync (19), docs lint passed. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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July 7, 2026 23:12
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The README's Current Support Snapshot says generated audits are the authority when prose disagrees, but runtime_execution_matrix.md records only sm_120's shipped `nvidia_mma` GEMM. My reconcile prose claimed the new generic CUDA + tensor-core lanes as executable, which disagrees with the cited dashboard. Root cause: those lanes run through the arbiter/emit subsystem (emit/nvidia_cuda.py + candidate.py + in-process nvcc), a different path from the execution-matrix executor registry — so they're hardware-proven by the plugin/perf/conformance test gates (test_nvidia_plugin.py, test_nvidia_perf_ratchet.py, test_conformance_execute_compare_nvidia.py), not recorded in the matrix, and a regen won't add them. Fix (README, MASTER_AUDIT, docs/README): scope the execution-matrix-authoritative rows to `nvidia_mma`, attribute the arbiter/emit + tensor-core lanes to their real proof surface (the test gates), and add "promote the arbiter/emit lanes into the execution matrix" as an explicit still-open item — which is the genuine gap. Doc-only. Frontmatter 8/8, drift gate in sync (19), docs lint passed. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Reconcile the all-up status with what's actually merged
The plan doc carried "landed" annotations for Workstreams C/D/E (PRs #286–#302), but the status surfaces had drifted behind the wave. This refreshes them — prose only; counts stay in the generated dashboards (Decision #26).
MASTER_AUDIT.mdmma.syncGEMM/flash-attn Tier-2 lanes the arbiter selects, via the shipped PTX launch bridge, all F4-gated + hardware-proven; Runtime/backend + ROCm rows note the generic plugin lanes + arbiter + x86 Zen 5backend/nvidia/NVIDIA_AUDIT.mdCOMPILER_REFACTOR_PLAN.md⬜⬜⬜→ landed (escape hatch lives in the D1forcepath + PR #298 test); E3 bullet annotated landedREADME.mdpython/tessera/compiler/emit/, NVIDIA/ROCm/x86 executing)docs/README.mdVerification
Doc-only. Frontmatter contract 8/8, generated-doc drift gate in sync (19), docs lint passed.
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