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D1/B1: bare-matmul op-kind + NVIDIA GEMM arbiter candidates (sm_120) - #293

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Jul 7, 2026
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@gstoner gstoner commented Jul 7, 2026

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Section B, item 1 — wire the emitted GEMM as a first-class arbiter candidate. The blocker you flagged (no bare-matmul op-kind in the D1 registry) is cleared. Verified on the live sm_120 box.

The blocker

The D1 candidate registry only had fused_region/attention/gated/pointwise op-kinds. A plain D = A @ B isn't a FusedRegion (that always carries ≥1 fused op), so the compiler-emitted mma.sync GEMM lane had nowhere to plug in.

What landed

  • fusion_core: MatmulRegion (bare GEMM, 16-bit storage / f32 accumulate) + verify_synthesized_matmul (arbiter-only F4 oracle, dtype-rounded reference) + a _round_to_storage helper; re-exported through the fusion facade.
  • candidate.py: OP_MATMUL op-kind + its (verify, run_matmul) map entry + a run_matmul method on the _as_runner adapter.
  • runtime.py: two 2D GEMM execution helpers — _nvidia_mma_gemm_2d (shipped libtessera_nvidia_gemm, row-major B) and _nvidia_ptx_gemm_2d (compiler-emitted ptx_emit via the launch bridge, col-major B), keyed by 16-bit dtype; + a bridge loader mirroring the shipped-GEMM one.
  • emit/nvidia_cuda.py: NvidiaMmaGemmShippedCandidate (Tier-3 hand-tuned) + NvidiaMmaGemmEmittedCandidate (Tier-2 emitted, aligned-only) under (nvidia, matmul); both F4-gated, f16 accuracy budget.

Behavior

Tier-priority picks the shipped lane by default (lead-safe, Decision #28); the E3 force hatch selects the emitted lane. NVIDIA now has its Tier-3 hand-tuned GEMM candidate (previously only reachable via the jit nvidia_mma executor) alongside the Tier-2 emitted lane.

Verified on sm_120 (RTX 5070 Ti)

Both lanes F4-verify + execute + match the dtype-rounded reference across bf16/f16 × 16×8×16 / 32×16×32 / 64×64×64; the arbiter selects shipped by default and force selects emitted. 152 passed / 135 skipped across the plugin+fusion suite; ruff + mypy clean; drift green.

Next (this section)

  • D2: measured autotune loop on sm_120 — replace tier-priority with real on-device latency per shape-bucket (lets the Tier-2 emitted lane win where faster). Now unblocked by this op-kind.
  • D3: fallback logging for NVIDIA.

🤖 Generated with Claude Code

Unblock the D1 arbiter for plain GEMM — the candidate registry only had
fused_region/attention/gated/pointwise, no bare matmul, so the emitted mma.sync
GEMM lane had nowhere to plug in.

* fusion_core: MatmulRegion (D = A @ B, 16-bit storage / f32 accumulate) +
  verify_synthesized_matmul (arbiter-only F4 oracle, dtype-rounded reference) +
  a _round_to_storage helper; re-exported through the fusion facade.
* candidate.py: OP_MATMUL op-kind + its (verify, run_matmul) map entry + a
  run_matmul method on the _as_runner adapter.
* runtime.py: two 2D GEMM execution helpers the candidates call —
  _nvidia_mma_gemm_2d (shipped libtessera_nvidia_gemm, row-major B) and
  _nvidia_ptx_gemm_2d (compiler-emitted ptx_emit via the launch bridge, col-major
  B), keyed by 16-bit dtype; + a bridge loader mirroring the shipped-GEMM one.
* emit/nvidia_cuda.py: NvidiaMmaGemmShippedCandidate (Tier-3 hand-tuned) and
  NvidiaMmaGemmEmittedCandidate (Tier-2 emitted, aligned-only) registered under
  (nvidia, matmul); both F4-gated, f16 accuracy budget.

Tier-priority picks the shipped lane by default (lead-safe, Decision #28); the E3
force hatch selects the emitted lane. So NVIDIA gains its Tier-3 hand-tuned GEMM
candidate (previously only reachable via the jit nvidia_mma executor) next to the
Tier-2 emitted lane. D2's measured loop (lets Tier-2 win where faster) is the
follow-on.

Live-proven on sm_120 (RTX 5070 Ti): both lanes verify + execute + match the
dtype-rounded reference across bf16/f16 x 16x8x16/32x16x32/64x64x64; arbiter
selects shipped by default, force selects emitted (test_nvidia_plugin.py).

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@gstoner
gstoner enabled auto-merge (squash) July 7, 2026 19:35

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Comment thread python/tessera/runtime.py
Ac = np.ascontiguousarray(A, store)
Bc = np.ascontiguousarray(B, store)
M, K = Ac.shape
_, N = Bc.shape

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P2 Badge Validate B's K dimension before launching GEMM

When run_arbitrated selects the shipped NVIDIA matmul candidate, mismatched rank-2 inputs such as A.shape == (M, K) and B.shape == (K2, N) with K2 != K reach this helper. This line discards K2 and passes K to the native C ABI, which then copies K*N elements from B even if the NumPy buffer only contains K2*N; that can overread host memory or silently compute against the wrong slice instead of raising like MatmulRegion.reference/the existing JIT path does. Check Bc.shape[0] == K before calling the C function.

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Comment thread python/tessera/compiler/emit/nvidia_cuda.py
@gstoner
gstoner merged commit 56ebd04 into main Jul 7, 2026
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gstoner deleted the nvidia/d1-matmul-op-kind branch July 7, 2026 22:58
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