docs(roadmap): single S-series closure plan + Tier-0 compiler foundation + native fused-kernel inventory - #187
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Plan for driving the remaining S-series primitives to real on-device execution on the two devices we can prove on today — x86 AVX-512 + ROCm gfx1151 (RDNA 3.5 WMMA). Corrects the "144 reference" framing to the per-device truth (the universal backend_kernel gate reads 0/474 by design): ~127 ops execute on both devices, ~171 on neither, ~10 ROCm-only (WMMA attention lanes needing an x86 partner). Triages the ~171 both-device gap into: - Tier 0 host/structural (layout_transform/indexing) → classify not_applicable, no kernel; - Tier 1 mesh-gated transport (collective/moe_transport) → stays gated; - Tier 2 easy elementwise/predicate → extend existing lanes; - Tier 3 composable (optimizer steps incl. fused AdamW, norm, complex/GA, losses); - Tier 4 new kernel families (attention, conv, sort/top_k, MLA loop_nest, RNG). Records the NATIVE (AVX-512 + RDNA WMMA) planned fused-kernel inventory — flash_attn / MLA / NSA / lightning / kimi / swiglu / fused AdamW / conv / sort / Philox RNG — the executable-now companion to the hardware-gated WGMMA/MFMA inventories (nvidia_cuda13 / rocm_mfma), aligned to the canonical family names guarded by test_kernel_inventory_and_lit_fixtures.py. Sequences phased PRs A→G using the per-family cadence proven across #180–#186. Linked from ROADMAP_AUDIT. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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| is to mark `backend_kernel = not_applicable` per op (Decision #25 — only after | ||
| verifying zero FLOP content), which closes the open count without inflating it. |
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If Phase A follows this directive for the listed reshape/cat/gather/scatter-style tensor ops, it will close backend_kernel rows without proving any x86/ROCm target path. The existing contract says backend_kernel stays partial until each backend ships a real hardware kernel (python/tessera/compiler/primitive_coverage.py), and the generated S-series status still treats every backend category as open by design; zero FLOPs is not the same as zero backend execution for copy/index/data-movement primitives. This would corrupt the generated counts instead of reflecting actual device coverage.
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Reframe Tier 0 from "just mark not_applicable" to the compiler-foundation workstream it actually is. Verified state: 28 of 33 structural ops have NO Graph IR op (only transpose/reshape/cast/select/masked_fill do) — they live only in the Python frontend + numpy runtime, so they can't enter a compiled pipeline, fuse, or lower to device movement. Autodiff VJPs are largely complete (incl. gather/ scatter/masked_fill — corrected an earlier mis-read); JVP deferred. §6 specifies what the compiler / runtime / stdlib each need: - 6.A Graph IR: ODS ops (reuse tensor/linalg dialect where it models the op; native tessera.layout/index ops only for roll/flip/repeat/tile/pack + ops that must carry a Tessera layout/distribution attr) + shape verify + canonicalizers + frontend emission. - 6.B Passes: view-vs-copy analysis, layout propagation/canonicalize, bufferization to strided memref, movement lowering — makes 0-view ops compile to stride rewrites (the real meaning of not_applicable). - 6.C Runtime: a backend-agnostic view descriptor ABI (generalize the Apple-only reshape_view), a strided-copy movement lane (0-move), and gather/scatter(+atomic) kernels (0-reduce) on x86 + ROCm via the proven cadence. - 6.D Contracts: formalize the UNSPECIFIED vmap/batching rule + sharding rule + flip transpose_rule (VJPs already exist). - 6.E Stdlib: pack/unpack, gather lowering-class fix, JVPs. Splits the kernel axis into 0-view (not_applicable), 0-move (movement lane), 0-reduce (real kernel) — so the disposition is honest per sub-class, not a blanket not_applicable. Sequenced F1→F5 (Graph IR → view passes → runtime ABI → gather/ scatter kernels → contracts). Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
…tier dives + Tier 5 Single closure plan: per-tier deep dives (§7) mirroring the §6 Tier-0 foundation lens (compiler / runtime / stdlib + kernel + deps + validation + disposition), plus a consolidated P0–P15 phase order (§8) that folds the compute phases together with the Tier-0 foundation steps F1–F5. - Tier 1 (transport): NOT greenfield — collective/moe ops already have ODS + mock-collective execution + sharding contract; the ONLY gap is real multi-GPU HW. Stays partial (single-rank ref + mock-mesh), ungates at Phase H. No kernel. - Tier 2 (elementwise/predicate): per-lane breakdown (unary+new digamma/lgamma poly cores, binary atan2/floor_div/mod, predicate isnan/isinf/isfinite float→i8, popcount VPOPCNTDQ, reduce/segment_reduce, ntk_rope on the rope lane). - Tier 3: optimizer steps are STATEFUL (need an m/v + step-counter runtime ABI, in-place multi-output) — fused AdamW called out; norm composes on reduce; complex reuses the FFT interleaved-f32 substrate; EBM/diffusion losses split by RNG dependency. - Tier 4: attention is mostly an x86-PARTNER problem (the 10 ROCm-only ops are attention WMMA lanes); state-recurrence variants reuse the selective_ssm scan substrate; NSA depends on top_k; RNG (Philox) unblocks the sampling losses. - Tier 5 (NEW): geometric_algebra / Clifford (18 ops) — distinct kernel pattern (table-driven bilinear contraction over the multivector Cayley table, not flat elementwise nor dense GEMM). CPU reference exists; ROCm is the headline gap. §8 P0–P15 front-loads honesty/structural-IR/elementwise/AdamW before the marquee attention+MLA work (which sits behind its substrate); transport (P15) is the only phase blocked on hardware this repo lacks. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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last_updated / audit_role: plan / plan_state: open — satisfies the test_audit_docs + test_docs_freshness frontmatter contract. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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One consolidated closure plan for driving the remaining S-series primitives to real, on-device-validated execution on the two devices this repo proves on today — x86 AVX-512 + ROCm gfx1151 (RDNA 3.5 WMMA). Adds
docs/audit/roadmap/S_SERIES_GAP_CLOSURE_PLAN.md(§1–§8) and links it fromROADMAP_AUDIT.md. Docs-only; drift clean.Framing correction (§1)
"144 reference" is the universal multi-target gate (
backend_kernel=completeneeds x86 and ROCm and NVIDIA and Apple → reads0/474by design). Per device: ~127 ops execute on both, ~171 on neither, ~10 ROCm-only (the WMMA attention lanes needing an x86 partner), ~1 x86-only. Counts stay dashboard-owned (Decision #25/#26).Triage — Tiers 0–5 (§2), each with a disposition
not_applicableafter §6.B compiles them to stride rewrites; 0-move (gather/pad/cat/…) → a memory-movement primitive; 0-reduce (scatter_add, nonzero) → real kernels.partial, ungates at Phase H. No kernel.§3 Planned fused-kernel inventory (native)
Per-device approach table (AVX-512 + gfx1151 WMMA
16×16×16) for matmul, flash_attn, MLA, NSA, lightning, kimi, swiglu_mlp, matmul_softmax_matmul, adamw_step, conv, quantized_matmul, Philox RNG, sort — the executable-now companion to the hardware-gated WGMMA/MFMA inventories, aligned to the canonical family names guarded bytests/unit/test_kernel_inventory_and_lit_fixtures.py(notes gfx1151 has no FP8/FP4 WMMA — that's CDNA4/RDNA4).§6 Tier-0 compiler foundation (the structural substrate)
The compiler/runtime/stdlib detail, file-grounded (§6.0 current-state table):
tensor/linalg(reshape→expand_shape, slice→extract_slice, pad→tensor.pad, gather/scatter); nativetessera.layout/tessera.indexonly where upstream lacks it or a Tessera layout/distribution attr is needed; verifiers + canonicalizers + frontend emission.(base, offset, shape, strides)in the C ABI; strided-copy movement lane; gather/scatter(+atomic) kernels via the feat(sparse): genuinely sparse kernels — spmm_csr/coo + sddmm + bsmm on both devices #180–feat(moe): mixture-of-experts compute — routed expert GEMVs on both devices #186 cadence.§7 Per-tier deep dives + §8 consolidated order
§7 applies the §6 lens (compiler / runtime / stdlib + kernel + deps + validation + disposition) to Tiers 1–5. §8 is the authoritative P0–P15 order — it weaves the Tier-0 foundation steps F1–F5 inline with the compute phases (P1=F1 Graph IR; P4=F2/F3 view passes + runtime ABI; P8=F4 gather/scatter; P14=F5 contracts). Front-loads honesty → structural IR → elementwise → fused AdamW before the marquee attention/MLA work; transport (P15) is the only phase blocked on hardware this box lacks.
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