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feat(s2): elementwise comparison kernels (eq/ne/lt/le/gt/ge) on gfx1151 + AVX-512 - #137

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s2/elementwise-compare
Jun 26, 2026
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s2/elementwise-compare

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@gstoner gstoner commented Jun 26, 2026

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Adds the S2 comparison family — the first compiled lane with a non-float (boolean) result — on both devices this box runs (gfx1151 + AVX-512). eq/ne/lt/le/gt/ge over float inputs → i8/bool output, with NaN semantics matching numpy. Follows the per-op-family quality bar: a real optimized device kernel and an on-device numerical test vs numpy.

ROCm (gfx1151)

  • tessera_rocm.compare ODS op + generate-rocm-compare-kernel pass — flat 2-operand per-element kernel: arith.cmpfextui i1→i8, memref<?xi8> output. NaN: ordered predicates (OEQ/OLT/OLE/OGT/OGE, NaN→false) except ne = UNE (NaN→true), matching np.not_equal/np.equal.
  • Runtime rocm_compare_compiled lane with asymmetric in/out element sizes (float in, 1-byte bool out) + executor table + execution-matrix catalog/row + _ROCM_COMPILED / _NUMERICAL_FIXTURES.
  • test_rocm_compare_compiled.py: 64 tests pass on gfx1151 across kind × dtype × shape incl. rank-3 + dedicated NaN-semantics test, plus a GPU-free codegen gate (6 kinds codegen → ROCDL, memref<?xi8> + cmpf asserted, bad kind rejected).

x86 (AVX-512)

  • avx512_compare_f32.cpp: _mm512_cmp_ps_mask (predicates _CMP_*_OQ / _CMP_NEQ_UQ) + _mm_maskz_set1_epi8(mask, 1) to expand the 16-lane mask to 0/1 bytes (AVX512BW+VL). C's native float operators already follow numpy's NaN rule, so the scalar reference uses them directly.
  • test_compare.cpp: validated standalone on the AVX-512 host — ALL PASSED (aligned/tail/small/wide/degenerate + NaN across all 6 kinds).

Honesty / scope

  • No x86:fused manifest slot claimed — Graph-IR→x86 lowering isn't wired yet (Decision Apple GPU MLA: weight-absorption decode (the bandwidth win) + KV-cache shape #25), matching the reduce/unary/binary lanes.
  • Closes the registry's comparison family (eq/ne/lt/le/gt/ge, all previously _planned). Regenerated drift dashboards (runtime_abi, runtime_execution_matrix, test_coverage) + ROCM_AUDIT.md. mypy + ruff clean.

Test plan

  • tessera-opt rebuilds; 6 kinds codegen + lower to ROCDL; bad kind rejected; f32,f32,i8,index signature
  • test_rocm_compare_compiled.py — 64 passed on gfx1151
  • x86 test_compare.cpp — ALL PASSED on AVX-512 host
  • drift gate + perf-doc count test green; mypy (ratchet 0) + ruff clean

🤖 Generated with Claude Code

…51 + AVX-512

Adds the S2 comparison family — the first compiled lane with a non-float
(boolean) result — on both devices this box runs. eq/ne/lt/le/gt/ge over float
inputs, i8/bool output, NaN semantics matching numpy (ordered everywhere except
ne, which is unordered-not-equal).

ROCm (gfx1151):
- `tessera_rocm.compare` ODS op + `generate-rocm-compare-kernel` pass: flat
  2-operand kernel, arith.cmpf (OEQ/UNE/OLT/OLE/OGT/OGE) -> extui i1->i8,
  memref<?xi8> output.
- runtime `rocm_compare_compiled` lane (_build/_execute with asymmetric in/out
  element sizes: float in, 1-byte bool out) + executor table + execution_matrix
  catalog/row; `_ROCM_COMPILED` + `_NUMERICAL_FIXTURES`.
- test_rocm_compare_compiled.py: validated on gfx1151 vs numpy across
  kind × dtype × shape incl. rank-3 + NaN semantics, + a GPU-free codegen gate.

x86 (AVX-512):
- avx512_compare_f32.cpp: `_mm512_cmp_ps_mask` (matching _CMP_*_OQ / _CMP_NEQ_UQ
  predicates) + `_mm_maskz_set1_epi8` to expand the mask to 0/1 bytes. C's native
  float operators already match numpy's NaN rule, so the scalar reference uses
  them directly. Validated standalone (test_compare.cpp, ALL PASSED incl. NaN).

No `x86:fused` manifest slot claimed — Graph-IR->x86 lowering still unwired
(Decision #25). Regenerated drift dashboards + ROCM_AUDIT.md.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@gstoner
gstoner merged commit 1de5d89 into main Jun 26, 2026
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@gstoner
gstoner deleted the s2/elementwise-compare branch June 26, 2026 18:18
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