using new fork of svd2rust

.vscode/settings.json

@@ -0,0 +1,12 @@
+{
+    "[rust]": {
+        "editor.defaultFormatter": "rust-lang.rust-analyzer",
+        "editor.formatOnSave": true
+    },
+    "rust-analyzer.check.allTargets": false,
+    "rust-analyzer.cargo.features": [
+        "g002",
+        "rt", 
+        "v-trap",
+    ]
+}

Cargo.toml

@@ -8,14 +8,18 @@ categories = ["embedded", "hardware-support", "no-std"]
 description = "With svd2rust generated peripherals for Freedom E310 MCU's."
 keywords = ["riscv", "register", "peripheral"]
 license = "ISC"
-rust-version = "1.61"
+rust-version = "1.76"
 
 [dependencies]
-critical-section = { version = "1.1.1", optional = true }
+critical-section = { version = "1.2.0", optional = true }
+riscv = "0.12.0"
+riscv-peripheral = "0.2.0"
+riscv-rt = { version = "0.13.0", features = ["no-interrupts"], optional = true }
 vcell = "0.1.3"
 
 [features]
-rt = []
+rt = ["riscv-rt"]
+v-trap = ["rt", "riscv-rt/v-trap"]
 g002 = []
 
 [package.metadata.docs.rs]

device.x

@@ -3,6 +3,14 @@ MEMORY
     RAM : ORIGIN = 0x80000000, LENGTH = 16K
 }
 
+/* Core interrupt sources and trap handlers */
+PROVIDE(MachineSoft = DefaultHandler);
+PROVIDE(_start_MachineSoft_trap = _start_DefaultHandler_trap);
+PROVIDE(MachineTimer = DefaultHandler);
+PROVIDE(_start_MachineTimer_trap = _start_DefaultHandler_trap);
+PROVIDE(MachineExternal = DefaultHandler);
+PROVIDE(_start_MachineExternal_trap = _start_DefaultHandler_trap);
+/* External interrupt sources */
 PROVIDE(WATCHDOG = DefaultHandler);
 PROVIDE(RTC = DefaultHandler);
 PROVIDE(UART0 = DefaultHandler);

settings.yaml

@@ -0,0 +1,52 @@
+riscv_config:
+  core_interrupts:
+    - name: "MachineSoft"
+      value: 3
+      description: "Machine Software Interrupt"
+    - name: "MachineTimer"
+      value: 7
+      description: "Machine Timer Interrupt"
+    - name: "MachineExternal"
+      value: 11
+      description: "Machine External Interrupt"
+
+  priorities:
+    - name: "P0"
+      value: 0
+      description: "Priority level 0"
+    - name: "P1"
+      value: 1
+      description: "Priority level 1"
+    - name: "P2"
+      value: 2
+      description: "Priority level 2"
+    - name: "P3"
+      value: 3
+      description: "Priority level 3"
+    - name: "P4"
+      value: 4
+      description: "Priority level 4"
+    - name: "P5"
+      value: 5
+      description: "Priority level 5"
+    - name: "P6"
+      value: 6
+      description: "Priority level 6"
+    - name: "P7"
+      value: 7
+      description: "Priority level 7"
+
+  harts:
+    - name: "H0"
+      value: 0
+      description: "Hart 0"
+
+  clint:
+    name: "CLINT"
+    freq: 32768
+    async_delay: false
+
+  plic:
+    name: "PLIC"
+    core_interrupt: "MachineExternal"
+    hart_id: "H0"

src/aonclk/lfrosccfg.rs

@@ -43,25 +43,21 @@ impl R {
 impl W {
     #[doc = "Bits 0:5"]
     #[inline(always)]
-    #[must_use]
     pub fn div(&mut self) -> DivW<LfrosccfgSpec> {
         DivW::new(self, 0)
     }
     #[doc = "Bits 16:20"]
     #[inline(always)]
-    #[must_use]
     pub fn trim(&mut self) -> TrimW<LfrosccfgSpec> {
         TrimW::new(self, 16)
     }
     #[doc = "Bit 30"]
     #[inline(always)]
-    #[must_use]
     pub fn enable(&mut self) -> EnableW<LfrosccfgSpec> {
         EnableW::new(self, 30)
     }
     #[doc = "Bit 31"]
     #[inline(always)]
-    #[must_use]
     pub fn ready(&mut self) -> ReadyW<LfrosccfgSpec> {
         ReadyW::new(self, 31)
     }

src/generic.rs

@@ -147,6 +147,7 @@ pub mod raw {
         }
     }
 
+    #[must_use = "after creating `FieldWriter` you need to call field value setting method"]
     pub struct FieldWriter<'a, REG, const WI: u8, FI = u8, Safety = Unsafe>
     where
         REG: Writable + RegisterSpec,
@@ -174,6 +175,7 @@ pub mod raw {
         }
     }
 
+    #[must_use = "after creating `BitWriter` you need to call bit setting method"]
     pub struct BitWriter<'a, REG, FI = bool, M = BitM>
     where
         REG: Writable + RegisterSpec,