Inconsistent 'results' with NMOS transistors in parallel

[dmblankncoril]

Given the Verilog design below (changing the '.txt' extenstion to '.v' since github doesn't like files with the '.v' extension), the LED has three states: On, Off, or Floating, depending on value of the switches instead of the expected On or Off:
a) All off -> LED On,
b) If only bits 0, 1, or 4 are On then the LED is Floating
c) If any of bits 2, 3, or 5 are On (bits 0, 1, 4 can be either) then the LED is Off
I've been working on creating the Open Collector 74xx designs ... it looked good until I connected 4 7401 outputs together and the results where inconsistent.
I'm guessing the problem is problem is in verga/value.c, joining multiple values in to the 'TRI1' value.
NMOS_tb.txt

thanks,
++dean