//: version "2.2"
//: property encoding = "utf-8"
//: property locale = "en"
//: property prefix = "_GG"
//: property title = "7401_tb.v"
//: property timingViolationMode = 2
//: property initTime = "0 ns"

`timescale 1ns/1ns

//: /netlistBegin main
module main;    //: root_module
reg [5:0] w12;    //: /sn:0 {0}(#:187,166)(#:146,166){1}
supply0 w52;    //: /sn:0 {0}(380,283)(380,275)(380,275)(380,267){1}
//: {2}(380,263)(380,219)(380,219)(380,245){3}
//: {4}(378,265)(367,265)(367,265)(359,265){5}
//: {6}(357,263)(357,253)(357,253)(357,209){7}
//: {8}(355,265)(343,265)(343,265)(335,265){9}
//: {10}(333,263)(333,191)(333,191)(333,188){11}
//: {12}(331,265)(321,265)(321,265)(311,265){13}
//: {14}(309,263)(309,162)(309,162)(309,162){15}
//: {16}(307,265)(298,265)(298,265)(288,265){17}
//: {18}(286,263)(286,241)(286,241)(286,145){19}
//: {20}(284,265)(263,265)(263,125){21}
tri1 w41;    //: /sn:0 {0}(357,192)(357,181)(378,181){1}
//: {2}(380,179)(380,157){3}
//: {4}(380,153)(380,140)(380,140)(380,134){5}
//: {6}(380,130)(380,117)(380,117)(380,110){7}
//: {8}(380,106)(380,104)(380,104)(380,88){9}
//: {10}(382,86)(395,86)(395,86)(407,86){11}
//: {12}(380,84)(380,71){13}
//: {14}(378,86)(263,86)(263,108){15}
//: {16}(378,108)(286,108)(286,128){17}
//: {18}(378,132)(309,132)(309,145){19}
//: {20}(378,155)(333,155)(333,171){21}
//: {22}(380,183)(380,206)(380,206)(380,228){23}
wire w36;    //: /sn:0 {0}(319,179)(229,179)(229,171)(193,171){1}
wire w31;    //: /sn:0 {0}(249,116)(210,116)(210,141)(193,141){1}
wire w32;    //: /sn:0 {0}(272,136)(224,136)(224,151)(193,151){1}
wire w35;    //: /sn:0 {0}(295,153)(233,153)(233,161)(193,161){1}
wire w2;    //: /sn:0 {0}(343,200)(215,200)(215,181)(193,181){1}
wire w5;    //: /sn:0 {0}(366,236)(214,236)(214,191)(193,191){1}
//: enddecls

  //: joint g4 (w41) @(380, 181) /w:[ -1 2 1 22 ]
  //: joint g44 (w52) @(286, 265) /w:[ 17 18 20 -1 ]
  //: joint g3 (w41) @(380, 155) /w:[ -1 4 20 3 ]
  //: joint g47 (w41) @(380, 132) /w:[ -1 6 18 5 ]
  //: DIP g2 (w12) @(108,166) /sn:0 /R:1 /w:[ 1 ] /st:32 /dn:0
  _GGNMOS #(2, 1) g1 (.Z(w41), .S(w52), .G(w5));   //: @(374,236) /sn:0 /w:[ 23 3 0 ]
  _GGNMOS #(2, 1) g39 (.Z(w41), .S(w52), .G(w35));   //: @(303,153) /sn:0 /w:[ 19 15 0 ]
  //: LED g49 (w41) @(414,86) /sn:0 /R:3 /w:[ 11 ] /type:0
  //: joint g6 (w52) @(357, 265) /w:[ 5 6 8 -1 ]
  assign {w5, w2, w36, w35, w32, w31} = w12; //: CONCAT g35  @(188,166) /sn:0 /R:2 /w:[ 1 1 1 1 1 1 0 ] /dr:0 /tp:0 /drp:0
  //: GROUND g41 (w52) @(380,289) /sn:0 /w:[ 0 ]
  //: PULLUP g45 (w41) @(391,37) /sn:0 /w:[ 13 ]
  _GGNMOS #(2, 1) g40 (.Z(w41), .S(w52), .G(w36));   //: @(327,179) /sn:0 /w:[ 21 11 0 ]
  //: joint g42 (w52) @(333, 265) /w:[ 9 10 12 -1 ]
  //: joint g46 (w41) @(380, 108) /w:[ -1 8 16 7 ]
  //: joint g5 (w52) @(380, 265) /w:[ -1 2 4 1 ]
  _GGNMOS #(2, 1) g0 (.Z(w41), .S(w52), .G(w2));   //: @(351,200) /sn:0 /w:[ 0 7 0 ]
  _GGNMOS #(2, 1) g38 (.Z(w41), .S(w52), .G(w32));   //: @(280,136) /sn:0 /w:[ 17 19 0 ]
  //: joint g43 (w52) @(309, 265) /w:[ 13 14 16 -1 ]
  _GGNMOS #(2, 1) g37 (.Z(w41), .S(w52), .G(w31));   //: @(257,116) /sn:0 /w:[ 15 21 0 ]
  //: joint g53 (w41) @(380, 86) /w:[ 10 12 14 9 ]

endmodule
//: /netlistEnd

//: /hdlBegin SN7401
//: interface  /sz:(97, 144) /bd:[ Li0>B4(128/144) Li1>A4(112/144) Li2>B3(96/144) Li3>A3(80/144) Li4>B2(64/144) Li5>A2(48/144) Li6>B1(32/144) Li7>A1(16/144) Ro0<Y4(64/144) Ro1<Y3(48/144) Ro2<Y2(32/144) Ro3<Y1(16/144) ] /pd: 0 /pi: 0 /pe: 1 /pp: 0
//: property pptype=0
//: enddecls
module SN7401(A1, A2, A3, A4, B1, B2, B3, B4, Y1, Y2, Y3, Y4);
  // 7401      14    4      Quad 2 Input NAND gate (OC) 5V/15mA
  input    A1, A2, A3, A4, B1, B2, B3, B4;
  output   Y1, Y2, Y3, Y4;

  wire     y1, y2, y3, y4;
  supply0  gnd;

  and      g1(y1, A1, B1);
  and      g2(y2, A2, B2);
  and      g3(y3, A3, B3);
  and      g4(y4, A4, B4);
  nmos #15   (Y1, gnd, y1);
  nmos #15   (Y2, gnd, y2);
  nmos #15   (Y3, gnd, y3);
  nmos #15   (Y4, gnd, y4);

endmodule
//: /hdlEnd


`timescale 1ns/1ns