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sycl: Update gate logic for Alchemist GPUs regarding OneDNN features. #26635

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Merged
ggerganov merged 6 commits into from
Aug 21, 2026
Merged

sycl: Update gate logic for Alchemist GPUs regarding OneDNN features. #26635

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161626d
feat: updated gating logic of fattn-onednn.cpp
HumerousGorgon Aug 5, 2026
17421e2
verified device types
HumerousGorgon Aug 5, 2026
b291b92
Update ggml/src/ggml-sycl/fattn-onednn.cpp
HumerousGorgon Aug 6, 2026
d388f31
Improved SPDA gate, added documentation.
HumerousGorgon Aug 6, 2026
044fb7b
Added arch var to reworked gate, fixing build errors.
HumerousGorgon Aug 9, 2026
8e55842
Fix trailing whitespaces.
HumerousGorgon Aug 12, 2026
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20 changes: 12 additions & 8 deletions ggml/src/ggml-sycl/fattn-onednn.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -21,14 +21,6 @@ bool ggml_sycl_flash_attn_ext_onednn_supported(const ggml_tensor * dst) {
if (!g_ggml_sycl_fa_onednn) {
return false;
}
// Battlemage (Xe2) only, for now. On other Intel archs oneDNN's fused SDPA returns wrong results
// for some shapes (e.g. head_dim=64 on Arc / xe_hpg) -- an oneDNN bug tracked upstream at
// https://github.com/uxlfoundation/oneDNN/issues/5510. Remove this hardware limitation once that
// is fixed; until then non-BMG archs fall back to the existing FA kernel.
const gpu_arch arch = ggml_sycl_info().devices[ggml_sycl_get_device()].hw_info.arch;
if (arch != gpu_arch::intel_gpu_bmg_g21 && arch != gpu_arch::intel_gpu_bmg_g31) {
return false;
}
const ggml_tensor * Q = dst->src[0];
const ggml_tensor * K = dst->src[1];
const ggml_tensor * V = dst->src[2];
Expand Down Expand Up @@ -60,6 +52,18 @@ bool ggml_sycl_flash_attn_ext_onednn_supported(const ggml_tensor * dst) {
}
}
}
const gpu_arch arch = ggml_sycl_info().devices[ggml_sycl_get_device()].hw_info.arch;
const bool is_bmg = (arch == gpu_arch::intel_gpu_bmg_g21 || arch == gpu_arch::intel_gpu_bmg_g31);
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const bool is_dg2 = (arch == gpu_arch::intel_gpu_dg2_g10 ||
arch == gpu_arch::intel_gpu_dg2_g11 ||
arch == gpu_arch::intel_gpu_dg2_g12); // verified that dg2_x works alongside acm_gx

if (!is_bmg && !is_dg2) {
return false; // unverified/untested arch: stay conservative
}
if (is_dg2 && K->ne[0] == 64) {
return false; // known-bad shape on this family
}
// Optional KV-length ceiling (GGML_SYCL_FA_ONEDNN_MAX_KV, 0 = unlimited). Escape hatch:
// very long sequences make the fused SDPA slow enough to risk the xe driver watchdog on
// some stacks; past the cap we fall back to the native FA kernel instead.
Expand Down