opencl: transpose the FA prefill K tile in local memory for perf optimization

[wanghqc]

Overview

This PR is to optimize the current FA OpenCL C kernels:

• The flash-attention prefill kernels (flash_attn_f32_f16 / _q8_0 / _q4_0) stage the K tile in local memory and the QK loop reads.
• For each step, several KV rows that are DK_VEC apart — i.e. one narrow 64-bit local read per row.
• Transpose that tile in local memory so the KV rows the loop walks together become adjacent: a pair (f16) is then one 128-bit read, halving the LDS issues for the exact same bytes.
• Arithmetic and FMA order untouched → bit-identical output.

Default-on at DK ≤ 128 (the geometry where the paired read is valid);

• kill switch GGML_OPENCL_FA_K_LDS_T=0.
• DK=256 stays on the original path (measured negative there).
• Layout-only. PPL/greedy bit-identical everywhere measured.
• TBO FLASH_ATTN_EXT counts are identical to base on every device tested.

Additional information

Earlier fleet data (pre-rebase content, unchanged kernels):

• Win on X1/X2/840, X1-85 pp4096 +8.6% / pp8192 +11.5%, 740 neutral.
• Intel NEO neutral +0.1% (2565/2565).
• No Adreno gate needed.
• Only cfg->dk <= 128.

device	correctness (TBO FLASH_ATTN_EXT)	perf vs base
Adreno X2-90 (asus-x2, native ARM64)	identical counts, 0 FAIL	pp4096 485.4 → 528.3 = +8.8%; tg32 neutral (−0.5%)
Adreno 840 (NX809J, NDK arm64)	2653/2653, identical to base	pp4096 +5.4..+8.6% (128–132 → 139.2); tg32 neutral

Requirements

• I have read and agree with the contributing guidelines Yes
• AI usage disclosure: Yes, prototyping and testing.