Add Q5_K ESIMD kernel - #26376
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Configure cmake build with -DGGML_SYCL_ESIMD=ON to enable. Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
While not an issue in the current version, this will become an issue when additional QK ESIMD kernels are added (such as Q2_K). Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
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Same as the others, I will rebase this once #25942 is merged. |
arthw
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Aug 1, 2026
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With gemma-4-E2B-it-Q5_K_M.gguf on B60
| Test | fa | Base t/s | Primary t/s | Increase Rate (Primary vs Base) |
|---|---|---|---|---|
| pp512 | 0 | 2154.07 | 2156.09 | 0.09% |
| pp512 | 1 | 2143.85 | 2133.25 | -0.49% |
| tg128 | 0 | 99.42 | 104.56 | 5.17% |
| tg128 | 1 | 99.12 | 103.82 | 4.74% |
Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
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Overview
This completes the usage of ESIMD for DMMV QK kernels begun in #25942.
Measured tg improvement of 1.04x to 1.35x (depending on hardware) using Qwen35-27B-Q5_K_M.
Additional information
Note: all measurements were captured with aicss-genai/fix-row-calculation (already merged in master) and aicss-genai/fattn-single-device-sync (better solution already merged in master, will only improve pp results below) merged as the parent branch predates those necessary patches.
PVC performance
Baseline
DMMV
ESIMD
B70 performance
Baseline
DMMV
ESIMD
Perplexity tests across wikitext, hellaswag, and winogrande showed no significant changes between baseline and ESIMD.
Requirements