Add DMMV ESIMD Q3_K kernel - #26251
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Configure cmake build with -DGGML_SYCL_ESIMD=ON to enable. Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
While not an issue in the current version, this will become an issue when additional QK ESIMD kernels are added (such as Q2_K). Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
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This is currently a draft built upon #25942, I will rebase and mark ready for review when that PR is merged. |
arthw
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Jul 29, 2026
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Qwen3-14B-Q3_K_M.gguf on B60:
export GGML_SYCL_PRIORITIZE_DMMV=0
export GGML_SYCL_ENABLE_ESIMD=1
| Test | fa | Base t/s | Primary t/s | Increase Rate (Primary vs Base) |
|---|---|---|---|---|
| pp512 | 0 | 92.19 | 99.59 | 8.03% |
| pp512 | 1 | 75.33 | 81.65 | 8.39% |
| tg128 | 0 | 4.43 | 8.57 | 93.45% |
| tg128 | 1 | 4.56 | 9.08 | 99.12% |
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@malsbat |
malsbat
marked this pull request as ready for review
August 4, 2026 16:36
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I have reached the open pull request limit, I will mark the others as ready for review once these get merged. |
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@malsbat We will merge them as soon! Thank you! |
CowboyTim
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Aug 16, 2026
* Add DMMV Q4_K and Q6_K ESIMD kernels Configure cmake build with -DGGML_SYCL_ESIMD=ON to enable. Signed-off-by: Todd Malsbary <todd.malsbary@intel.com> * Refactor ESIMD kernels to share common code Signed-off-by: Todd Malsbary <todd.malsbary@intel.com> * Move control of ESIMD from compile to runtime Signed-off-by: Todd Malsbary <todd.malsbary@intel.com> * Use ESIMD by default when available Signed-off-by: Todd Malsbary <todd.malsbary@intel.com> * Fix possible error when using ESIMD by default While not an issue in the current version, this will become an issue when additional QK ESIMD kernels are added (such as Q2_K). Signed-off-by: Todd Malsbary <todd.malsbary@intel.com> * Add explicit unroll to ESIMD kernels Signed-off-by: Todd Malsbary <todd.malsbary@intel.com> * Tidy up ESIMD kernels a bit Signed-off-by: Todd Malsbary <todd.malsbary@intel.com> * Add DMMV Q3_K ESIMD kernel Signed-off-by: Todd Malsbary <todd.malsbary@intel.com> --------- Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
brittlewis12
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Aug 17, 2026
* Add DMMV Q4_K and Q6_K ESIMD kernels Configure cmake build with -DGGML_SYCL_ESIMD=ON to enable. Signed-off-by: Todd Malsbary <todd.malsbary@intel.com> * Refactor ESIMD kernels to share common code Signed-off-by: Todd Malsbary <todd.malsbary@intel.com> * Move control of ESIMD from compile to runtime Signed-off-by: Todd Malsbary <todd.malsbary@intel.com> * Use ESIMD by default when available Signed-off-by: Todd Malsbary <todd.malsbary@intel.com> * Fix possible error when using ESIMD by default While not an issue in the current version, this will become an issue when additional QK ESIMD kernels are added (such as Q2_K). Signed-off-by: Todd Malsbary <todd.malsbary@intel.com> * Add explicit unroll to ESIMD kernels Signed-off-by: Todd Malsbary <todd.malsbary@intel.com> * Tidy up ESIMD kernels a bit Signed-off-by: Todd Malsbary <todd.malsbary@intel.com> * Add DMMV Q3_K ESIMD kernel Signed-off-by: Todd Malsbary <todd.malsbary@intel.com> --------- Signed-off-by: Todd Malsbary <todd.malsbary@intel.com>
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Overview
Continuing the work in #25942 to add the DMMV ESIMD Q3_K kernel.
Additional information
Note: all measurements were captured with #25741 applied locally as the parent PR does not include the newer upstream fix. This only affects pp numbers which are not the important part of this PR.
Performance on B70
export GGML_SYCL_PRIORITIZE_DMMV=0
export GGML_SYCL_ENABLE_ESIMD=0
./build/bin/llama-bench -m /models/Qwen3-14B-Q3_K_M.gguf -ngl 100
export GGML_SYCL_PRIORITIZE_DMMV=1
export GGML_SYCL_ENABLE_ESIMD=0
./build/bin/llama-bench -m /models/Qwen3-14B-Q3_K_M.gguf -ngl 100
export GGML_SYCL_PRIORITIZE_DMMV=0
export GGML_SYCL_ENABLE_ESIMD=1
./build/bin/llama-bench -m /models/Qwen3-14B-Q3_K_M.gguf -ngl 100
Perplexity
Requirements