llama : stage mmap uploads on integrated GPUs - #26023
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Fully offloaded mmap models pass pageable file mappings directly to backend tensor uploads. On integrated GPUs, large files can exhaust temporary pinning and make model loading effectively stall. Reuse the existing pinned upload ring for eligible full-offload IGPU models, read chunks directly from the GGUF files, and suppress eager mmap prefetch on this path. Preserve existing fallbacks for partial offload, dGPU, mlock, check-tensors, and unsupported backends. Fixes ggml-org#15018 Reported-by: kyuz0 Assisted-by: GitHub Copilot Signed-off-by: liminfei-amd <91481003+liminfei-amd@users.noreply.github.com>
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IMO the correct solution here is to not default to mmap on integrated GPUs and to discourage using it for them, since it serves no purpose here unless the backend supports directly working with the mmapped data. We plan to look into that after #20834 lands. |
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@0cc4m you need mmap to use models bigger than your available RAM :) @liminfei-amd just a note that this sidesteps a ROCm bug: ROCm/ROCm#6501 - I've verified with the new experimental HRX engine with their bindings for HIP and it mmaps the model without problems. |
It doesn't work unless you access the pages directly from the GPU, which currently you can't, as far as I know, at least on CUDA/ROCm and Vulkan. |
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Wdym "it doesn't work", I just ran a 220GB quant on my Strix Halo :P |
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It doesn't work because the backend currently has to copy the mmapped data into GPU-visible (pinned) memory, instead of directly using the mmapped memory pages. |
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But those are two different meanings of "it doesn't work". It works in the sense that you can actually run a model that has more than your VRAM, which you can't do with any of the other memory allocation modes. It doesn't work in the sense that it's slower than it could be with direct memory access. |
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Yes, I suppose that is true, though I do not really know what it does if you try to mmap a model larger than your available shared RAM into an iGPU system. AFAIK it loads the file into RAM cache, then tries to copy each chunk into the same RAM, which is gonna OOM eventually. Did you partially offload when you tried that? |
+1 for |
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Thanks for the feedback and clarification on the preferred direction. The staged upload path is effective, but I agree that the new load-mode framework from #20834 is the better place to handle the default behavior for UMA systems. I’m closing this PR in favor of that direction. The underlying ROCm mmap issue remains tracked in ROCm/ROCm#6501, and the validation results here can still be useful if a staged fallback is needed later. |
Overview
Fixes #15018.
Fully offloaded models on integrated GPUs currently upload mmap-backed tensor
data directly from the file mapping. On large models this can enter an extreme
pageable-memory transfer path: in an exact-model reproduction with the reported
82.36 GiB model, loading stopped making progress at 34%, while
--no-mmapcompleted normally.
For eligible full-offload IGPU loads, read the GGUF data into the model
loader's existing pinned staging buffers and upload it asynchronously with
events. Disable eager whole-file mmap prefetch only for this path so the model
is not read twice.
CPU, discrete-GPU, partial-offload,
--mlock,--check-tensors, and backendswithout the required async, host-buffer, or event capabilities retain their
existing paths and fallbacks.
Additional information
Validated with the original 82.36 GiB Llama-4 Scout Q6_K model on gfx1151:
in 40.54 seconds with about 493 MiB peak RSS
RSS
logits on HIP and Vulkan
--mlock, and--check-tensorscontrols preserved their existing behavior
The triggering workload requires a model larger than 64 GiB and a large-UMA
IGPU, so it is not practical as a normal automated regression test.
@kyuz0 @pwilkin , could you please test this on the original HP Z2 Mini G1a / Fedora 42
setup with default mmap and full offload, preferably using the same Llama-4
Scout model, and confirm whether loading now reaches 100% normally?
Requirements
This is an experimental, AI-generated code change, reviewed by AMD engineers before submission.